Intel Cyclone® V SE 5CSXFC6D6F31C6N - maximum frequency

[MLaus3]

Hi there!

I want to do a 8192-FFT. I am searching for an eval board which fits my requirements.

I found the DE10-Standard Development Kit by Terasic with a Intel Cyclone® V SE 5CSXFC6D6F31C6N device.

In Chapter 3.5 (Clock Circuitry) it says:

Figure 3-13 shows the default frequency of all external clocks to the Cyclone V SoC FPGA. A

clock generator is used to distribute clock signals with low jitter. The four 50MHz clock signals

connected to the FPGA are used as clock sources for user logic. One 25MHz clock signal is

connected to two HPS clock inputs, and the other one is connected to the clock input of Gigabit

Ethernet Transceiver. Two 24MHz clock signals are connected to the clock inputs of USB

Host/OTG PHY and USB hub controller. The associated pin assignment for clock inputs to FPGA

I/O pins is listed in Table 3-5.

So am I right that the maximum clock frequency is limited to 50 MHz?

I already started a test design with Quartus Prime and selected the exact Cyclone V device and there I was able running frequencies up to 100 MHz..

I need a maximum frequency of 75 MHz. Is that possible with this FPGA-device?

Thank you in advance.

Best regards

Max

[AR_A_Intel]

Hi Sir

Welcome to INTEL forum. Based on my understanding, Yes, CV FPGA support 75MHz input clock frequency you can check out below CV datasheet spec to find out more about CV FPGA capability

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-v/cv_51002.pdf

For question regarding 75MHz input clock frequency be set in DE-10 board, I’m not sure. The DE-10 Board belong to Terasic. It would be better if you could contact Terasic for enquiry related to Terasic board. https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=12&No=20  

Please accept my apologies for not being able to assist you fully as this is out of my expertise.

[AR_A_Intel]

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[johnswenson1]

The Cyclone V SoC contains several PLLs which can convert the 50MHz clock input into pretty much anything you want. You access a PLL with the altpll IP core in Quartus. The main parameters you will need to set are multiplication factor and the division factor. To get 75MHz from 50MHz you need a multiplication factor of 3 and a division factor of 2. (50MHz X 3) /2 = 75MHz.

You can go much higher frequency than that if you want.

If you have an external clock that is already the frequency you want you can just bring it in to one of the GPIO pins.

In either case you should create design constraints that specify the clock net in your HDL (output of PLL, or GPIO pin) And specify the clock period. The optimizer can use this information to properly build the clock network for you. The software is actually smart enough to figure out what the actual clock pins are, but it can't figure out what frequency they are, so a design constraint is a really good idea. For such a low frequency you can probably get away with a base clock (the 50MHz) and the PLL output.

John S.