In order to extend pcie connector from end point to host, I have used the extension cable adapter including ( host gen3 switch based adapter, ipass cable 3m and an endpoint adapter).
I bought them from OSS, here are the links products used:
With above system setup, I am facing a problem that if FPGA bit file programmed to internal RAM and run from there, when host boots up, it could not detect FPGA card ( neither gen3, nor gen2/gen1), very few time host detected fpga card, not stable. Looks like there is a problem during link training btw host and endpoint device.
However it is working perfectly when insert fpga card directly to host system without extension adapter. ( With above set-up, it has only worked when FPGA bit file is programmed to ASx4 Flash, for testing purpose I just would like to programmed to fpga internal RAM only).
I have discussed with OSS technical team, it seems the problem with Arria 10 only.
With the same set-up, I have changed to Cyclone V GT dev kit, pcie x4 gen2, it works no matter whether FPGA bit-file in Flash or internal RAM.
Anyone has faced this problem earlier, please share your solution.
Do you see the link-up problem if you program the FPGA first, and then perform a reboot of the host PC?
You may also need to capture the signals below to understand what is going on during the link training:
I observed power/link leds from both host/target adapter cards, they were at the right states, nothing abnormal, but endpoint device could not been detected. I haven't probe the signals as you suggested, I have also planned for the next steps.
I have tried to start-up host system right after FPGA bit file programed completely ( when Quartus programmer in between 95% to 100%), since I thought of asynchronous issue. FPGA gen3 card could been detected some times, but not always.
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