I have created a design with 3 x 64-bit non-prefetchable BAR,
BAR0-1, has 32k RAM (32K space)
BAR2-3 has 32K RAM (64K space)
BAR 4-5 has 32K RAM (64K space)
used Quartus pro 19.4 for implementation
The target device is Stratix 10 DX kit (Device 1SD280PT2F55E2VGS1)
The design was a modified version of Example design of Intel FPGA P-Tile Avalon Memory Mapped (Avalon-MM) IP with onchip RAM and DMA.
The following modifications were done to this example design
1) Changed the BAR configurations as given above
2) Disabled DMA controller
3) Added 2 More onchip RAMs
4) Connected from BAR Interpreter to all the Onchip RAMs.
5) added flip-flops to the BAR interpreter block.
I was able to write to the BARs but the data was going to all the memory locations, an immediate read after write retrieves all ff's, but on reboot I can see memory written with the values but all the memories return read data as same value.
Please help me understand the issue.
Attached the system view, address map and the entire archive of the project.
Are you using the driver that comes with the example design? I have done a quick check, the read/write memory operation is not working, and already feedback to the Intel PCIe IP engineering team to resolve it.
Could you please use the v19.3 example design instead of v19.4? There is a problem in v19.4, it impact the DMA test, as well as memory read/write test. This problem will be fixed in the next Quartus version release.