Intel HW FAE for FPGAs?

[BigE]

Does anybody know how to get in touch with an Intel HW FAE for design support? 

I've been trying for a month now, and I keep getting the runaround, passed around from one person to the next when I try to email customer support. They even told me to ask Digikey or Mouser or another distributor for support! LOL. The competition is looking very enticing at this point. 

I'm trying to add DDR3 or even DDR4 to a TX series Stratix 10 device HPS and am looking for help and feedback. The complex series of "datasheets" (I think I've looked at about 20 now) aren't very helpful. Most of the information is around the FPGA code, not the HW implementation, and none of the PDFs look like a real datasheet for a specific part. Information is scattered across a dozen documents, and you have to cross reference back and forth, trying to guess at the correct solution, hoping for the best. 

I've searched app notes and only found a really old app note for a DDR3 - 533 implementation on a Stratix V. I've looked at reference designs, and at this point, my best effort is to try to translate a 64b implementation on a GX series part. Cross my fingers and spend $250k in taping out a board. 

Now, I *know* there is some FAE at Intel whose job it is to help people like me, and I'm sure they are great at their job. Finding that person is the hard part. :-). 

[ak6dn]

Your avatar tag indicates you are an Intel Employee, correct?

And you can't track down an FAE for Intel FPGAs?

Welcome to 2020.

[BoonT_Intel]

Hi

I believe you are seeking board development for DDR3 and DDR4 in the Stratix device?

We are unable to provide any board design support, but we can guide you for some reference material.

For the schematic, you can refer to the development kit material:

Devkit reference- https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-fpga.html

Schematic- https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/stratix10/fpga/s10gx_pcie_devkit_revD.pdf

For board design, you may refer to DDR4 Board Design Guidelines chapter for the S10 EMIF UG.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-emi.pdf#page=231

hope this helps.

[BoonT_Intel]

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

[sstrell]

This online training (the first two parts of the series of 4 mostly) goes into detail on integrating an EMIF, including how you must add the separate EMIF IP and connect it to the HPS in Platform Designer through a dedicated conduit interface enabled in the HPS IP parameters.

https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1121.html

https://www.intel.com/content/www/us/en/programmable/support/training/course/omem1122.html

Check those out and let us know if they help explain things.