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Intel High-Speed RS Decoder

shishirkc
Beginner
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I have successfully setup up the HS RS Encoder and its simulation setup to work along with a UVVM Testbench. I tried to setup the HS RS Decoder in a similar manner for simulation, but encountered the following warnings, because of which the outputs are not being driven.

 

# ** Warning: (vsim-8684) No drivers exist on out port /tb_hs_rs_decoder/i_test_harness/i_hs_rs_decoder/highspeed_rs_0/decoder/comp_poly/generate_inverses/inverse_of_alpha(8)(8 downto 1), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /tb_hs_rs_decoder/i_test_harness/i_hs_rs_decoder/highspeed_rs_0/decoder/comp_poly/value_of_inv(8)(8 downto 1).
# ** Warning: (vsim-8684) No drivers exist on out port /tb_hs_rs_decoder/i_test_harness/i_hs_rs_decoder/highspeed_rs_0/decoder/comp_poly/generate_inverses/inverse_of_alpha(7)(8 downto 1), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /tb_hs_rs_decoder/i_test_harness/i_hs_rs_decoder/highspeed_rs_0/decoder/comp_poly/value_of_inv(7)(8 downto 1).
# ** Warning: (vsim-8684) No drivers exist on out port /tb_hs_rs_decoder/i_test_harness/i_hs_rs_decoder/highspeed_rs_0/decoder/comp_poly/generate_inverses/inverse_of_alpha(6)(8 downto 1), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /tb_hs_rs_decoder/i_test_harness/i_hs_rs_decoder/highspeed_rs_0/decoder/comp_poly/value_of_inv(6)(8 downto 1).
# ** Warning: (vsim-8684) No drivers exist on out port /tb_hs_rs_decoder/i_test_harness/i_hs_rs_decoder/highspeed_rs_0/decoder/comp_poly/generate_inverses/inverse_of_alpha(5)(8 downto 1), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /tb_hs_rs_decoder/i_test_harness/i_hs_rs_decoder/highspeed_rs_0/decoder/comp_poly/value_of_inv(5)(8 downto 1).
# ** Warning: (vsim-8684) No drivers exist on out port /tb_hs_rs_decoder/i_test_harness/i_hs_rs_decoder/highspeed_rs_0/decoder/comp_poly/generate_inverses/inverse_of_alpha(4)(8 downto 1), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /tb_hs_rs_decoder/i_test_harness/i_hs_rs_decoder/highspeed_rs_0/decoder/comp_poly/value_of_inv(4)(8 downto 1).
# ** Warning: (vsim-8684) No drivers exist on out port /tb_hs_rs_decoder/i_test_harness/i_hs_rs_decoder/highspeed_rs_0/decoder/comp_poly/generate_inverses/inverse_of_alpha(3)(8 downto 1), and its initial value is not used.
# Therefore, simulation behavior may occur that is not in compliance with
# the VHDL standard as the initial values come from the base signal /tb_hs_rs_decoder/i_test_harness/i_hs_rs_decoder/highspeed_rs_0/decoder/comp_poly/value_of_inv(3)(8 downto 1).

 

Is this a known issue/ can it be corrected? I have source the correct msim_setup.tcl and called the ld command.

 

I tried to verify this on the board but on the Signal Tap I observed dec_fail for every packet. To check what is going wrong, I need the simulation setup, which is not possible because of the above errors.

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