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Intel Quartus Prime 21.1 error about peak virtual memory 4745 megabytes(DE1-SoC)

areebTAG
Beginner
422 Views

Hi,

 

I am trying to implement a HPS-FPGA design using DE1-SoC. However when I try to add my VHDL code to platform design, after "analyse synthesis files" I get an error about peak virtual memory. I tried to google this but cannot much find useful information about this. I uploaded a screenshot of the error shown. 

I also attached my VHDL file. It has been tested many times in Questasim and works as expected, but now is the time for synthesis. 

Minor question:  I used process(all) in my VHDL design, this only works in VHDL 2008. Since a sensitivity list in a process is ignored while synthesis I am assuming this would not be a problem?

(Previously I had some issue with my browser which prevented me from logging into these forums, but now I will try my best to respond to messages ASAP).

 

areebTAG_0-1650539793090.png

 

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3 Replies
EBERLAZARE_I_Intel
398 Views

Hi,


Could you provide me your whole design that you see this error?


areebTAG
Beginner
390 Views

Hi,

This error is fixed by changing the sensitivity of the process(all) to including signals. The sensitivity list in VHDL only supports "all" in VHDL 2008 which is not available in Quartus Prime Lite. 

Please close this question, the problem is fixed.

 

EBERLAZARE_I_Intel
361 Views

Hi,


Thanks for the update. Glad your issue is resolved.


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