As I understand it, you have some inquiries related to p and n trace length matching on the board. For your information, you should ensure matching length for the board trace for XCVR p/n pins. Sorry as I do not have insight into the design of the S10 devkit layout and could not further comment on that. However, you should ensure matching length on your board.
I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.