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Intel Stratix 10 MX FPGA HBM issue

LoveZJT
Beginner
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We find that the HBM on Intel Stratix 10 MX FPGA fails to calibrate successfully. After providing clock and releasing reset, the port local_cal_success is low and local_cal_fail is high. We also use the board test system to test it, but the Test Status is always running as shown below. Is this result correct?

hbm.png

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AdzimZM_Intel
Employee
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Hello,


May I know which design that you used to perform the test?


May I see the calibration status signals as well?


How long does the BTS keep running?


Regards,

Adzim


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LoveZJT
Beginner
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We use the BTS of design files on Intel website, and it keeps running 32h as shown below.

In these files, there is two example designs, hbm_top and hbm_bottom. In the project, we only integrate a additional signal tap to watch local_cal_success and local_cal_fail, but the result shows that local_cal_success is low and local_cal_fail is high.

 

hbm.png

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AdzimZM_Intel
Employee
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Hello,


How many devkit that you observed the calibration failure?


Can you check the HBM2 power rails and HBM2 clock frequency & quality?


Regards,

Adzim


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LoveZJT
Beginner
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I have only one devkit and it shows the calibration failure.

 

I config a new HBM2 ip and generate its example design. In this project, I add two counters whose clock is hbm_0_example_design_wmc_clk_0_clk and core_clk_iopll_ref_clk_clk respectitively as shown below.

 

In addition, I add a In-System Sources and Probes Editor to source three reset signals, core_clk_iopll_reset_reset_lxl, hbm_0_example_design_wmcrst_n_in_reset_n_lxl and hbm_only_reset_in_reset_lxl, which are connected to core_clk_iopll_reset_reset, hbm_0_example_design_wmcrst_n_in_reset_n, hbm_only_reset_in_reset ports of HBM2 ip respectitively. And it can probe the above counters, lock signal of PLL and calib status signals.

 

After programming sof to the board, firstly I give a low > high > low pulse to core_clk_iopll_reset_reset_lxl to enable PLL. Then I drive hbm_0_example_design_wmcrst_n_in_reset_n_lxl be high. Lastly I assert and then deassert hbm_only_reset_in_reset_lxl. The reset sequence is recommended in user guide

 

It shows that the two counters can increase normally, and the PLL is locked. But, the local_cal_success is low and local_cal_fail is high.

 

The frequency of PLL output clock is 250MHz and memory clock frequency is 600MHz. 

 

So the current problem is the example design of HBM2 IP fails to calibrate on Stratix 10 MX FPGA.

 

I am new in Intel FPGA design so this question would be an easy one for experts.

 

By the way, are there any other reference designs of HBM2 IP on Stratix 10 MX FPGA?

 

hbm.png

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AdzimZM_Intel
Employee
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Hello,


Thanks for sharing your debugging steps in details.


Do you have any tool that can be used to check the signal on board?

Usually we will check the clock is stable and voltage is stable or not.

If you can perform the same, kindly share the results of your finding.


Other than generated example design and development kit design, you can find some reference design in FPGA Design Store.

Link: https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-examples/design-store.html?q=hbm&s=Relevancy


What is your device ordering code?


Regards,

Adzim


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AdzimZM_Intel
Employee
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As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


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