I am using the Stratix 10 MX FPGA (8 G) - 1SM21BHU2F53E1VG. I am trying to use the Low latency 100G Ethernet IP Core to send ethernet packets over QSFP28 and I am having difficulty retrieving the IP and MAC addresses.
I saw in the Stratix 10 MX User Guide on page 71, section 5.3.2, it mentions the Sys Info Tab should contain the MAC address, however, it doesn't show up on the boardtestsystem.exe.
Is there a way to find out the MAC and IP addresses on the board?
Stratix 10 MX User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-intel-s10-mx-devl-kit...
Low Latency 100G IP Core User Guide: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_s10_ll_100gbe.pdf
The IP address stands for Internet Protocol Address, this does not come from the LL 100G Ethernet IP.
For the LL 100G Ethernet IP, as per the user guide, I don't see there is any register for the user to configure the MAC address, and this IP does not perform the "address check". The packets that forward from the LL 100G Ethernet IP to the user interface include the destination/source MAC address where the user can create custom logic to check/process it accordingly, therefore, the MAC IP address can be defined in the user logic but NOT within the IP. Please refer to figure 8 in the link below for the RX client frame.
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