I would like to link the DE2-115 to my PC and need to implement a simple protocol not taking away too many resources, so I thought to use GigE.I would like to interface the MARVEL chip directly with a simple MAC core for basic ethernet connection, possibly only UDP. Did anybody do this already?
Hm, It seems I have to clarify:I allready have a DE2-115 (with it's two MARVEL Alaska 88E1111) and like to program them - but directly with simple VHDL, meaing no MAC chip, no NIOS, no commercial core, no Altera ETH. I just need a slim and fast connection to the PC, possibly just UDP with a simple protocol to move data. For the first, it is sufficient to move data upwards from the FPGA to the PC. Does anybody know a project for this? I had a llok at the OC MAc but this is allready too much.
Yes you will need to write a MDIO master to be able to configure the PHY chip first. Note that the PHY datasheet isn't publicly available and you have to sign a rather restrictive NDA with Marvell if you want to get hold of it. You can go around it though and can have a look at the ALtera Nios dirver to see how the chip is initialized.Then you can directly connect a custom design to the PHY's RGMII interface. Of course you will have to generate/detect the preamble part of the packet and handle all the Ethernet protocol yourself, and probably add a MAC/protocol filter on the input side because a PC is very talkative a lot when you connect something to its Ethernet port ;)
I did this on the DE2-115, writing my own controllers, and made some observations on the way:1. The PHY is hardwired on the board to autonegotiate a link, it will do this before and after a hardware reset. Just insert a network cable and it works. 2. You can control the chip using the two basic management registers over MDIO, which is pretty straightforward. Use a statemachine that read/writes off the MDIO port@MDC clock. 3. In Gb mode tx and rx data is in double data rate. TX/RX is done like this, http://www.hp.com/rnd/pdfs/rgmiiv1_3.pdf (http://www.hp.com/rnd/pdfs/rgmiiv1_3.pdf) M.
Hello all, thanks for the information. I will come back to this now. I have the data sheet of the PHY and also know about MDIO IF. The question is only, what I do have to do, to get the PHY ready for sending.( I have experience with former projects regarding Xilinx Virtex + PowerPC and Spartan + MAC, but I did not send data directly to PHYs withut a MAC yet. For test purposes, I tried to activate the packet sender and the auto loop function available with the PHY in the last project but did not succeed, however. I did not find out finally, if it was a config problem or a hardware problem of that particular platform.)Assuming, the DE2-115 is ok and working, I want to repeat this now for Altera Cyclone IV - as said, without a MAC. I found that basic configuration can be achieved by only the hard wired config if done correctly. Now I wonder, how I can establish a logical link to a switch?
There shouldn't be a lot to do to the PHY to get it up running. The Marvel is very picky about its reset signal, but except for that, it should automatically auto-negotiate when going out of reset. Using the MDIO interface you should first interrogate the autonegotiation status and find what speed was negotiated, as the PHY interface will be different between BASE100-TX and gigabit, for example. Then configure the PHY to the correct interface (GMII, RGMII... I don't remember how it is connected on the kit). Also note that there is a clock phase shift option, just check that you use the correct setting, one matching the timing requirements for the project.Other than that, as long as you send a packet with a valid Ethernet header the switch should accept and retransmit it.
I used a lot of trial and error when I got the Cyclone III development kit, because at first no example with Ethernet was delivered with the kit and we were on our own. IIRC contrary to other PHYs the Marvel doesn't generate an automatic reset at power up, and needs a real reset signal from the FPGA or it will be in a strange state. Besides this reset signal needs to be at least as long as what they ask in the datasheet (10ms and 10 valid clock cycles) and you must wait a further 5ms before accessing the MDIO registers.
> 5ms before accessing the MDIO registers.Wowm that could be an important piece on information. Never took care about that so far. But could explain some funny effects I observed with this special PHY.
--- Quote Start --- Yes you will need to write a MDIO master to be able to configure the PHY chip first. Note that the PHY datasheet isn't publicly available and you have to sign a rather restrictive NDA with Marvell if you want to get hold of it. You can go around it though and can have a look at the ALtera Nios dirver to see how the chip is initialized. Then you can directly connect a custom design to the PHY's RGMII interface. Of course you will have to generate/detect the preamble part of the packet and handle all the Ethernet protocol yourself, and probably add a MAC/protocol filter on the input side because a PC is very talkative a lot when you connect something to its Ethernet port ;) --- Quote End --- Could you please tell me where the altera nios driver I need to look at is located and what it is called? I have not had any luck in locating the Marvell datasheet and I need to see how the 88E1111 is initialized. Thanks, Phil
In Quartus 11.1, you need to look at the file C:\altera\11.1\ip\altera\triple_speed_ethernet\lib\sopc_builder\altera_triple_speed_ethernet\HAL\src... and the functions marvell_phy_cfg, marvell_cfg_gmii, marvell_cfg_sgmii and marvell_cfg_rgmii, depending on the interface you use.It should be in a similar path on the other versions of Quartus.