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ABren1
Beginner
353 Views

Is it possible to initialize external RAM (ERAM) from the JTAG .sof or EPCS .pof file?

(i) By modifying the BSP to include the new region and section that points to ERAM

(ii) Include in NIOS2 code declaration of global variable and instantiation of variable in that section using "__attribute__". (A bitmap mapped as unsigned char[]).

My project tool path actions include : QSys/BSP Editor/Eclipse BSP + application/Quartus/Programmer/nios-terminal.

Observations: My quartus project builds successfully, however printf's to the nios-terminal of external ERAM contents don't agree with the values that I initialized in my C code suggesting they didn't get initialised. The .objdump file contains all the default sections and my new section with its hex dump in the file and it appears correct. When I view the onchip_mem.hex file it only contains records with addresses for onchip RAM at: 0x2000xxxx. There are no 0x3ff8xxx to 0x3ffc000 ERAM addresses in that file which leads me to the conclusion that the code in the .hex file or .sof file doesn't include a bootloader, alt_load() or something similar.

I have searched the forums for some description of the boot method used and whether this is even possible with a .sof via JTAG and how to initialize ERAM from bootup without any success. Is the ERAM only initialised with a true EPCS .pof file? Any ideas?

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12 Replies
JohnT_Intel
Employee
101 Views

Hi,

 

May I know what do you mean by external RAM? is it external DDR memory? May I know what FPGA are you using?

ABren1
Beginner
101 Views

​External SDRAM connected to NIOS2 System by SDRAM Controller. Have tested Ram by writing to all locations of full map.

Cyclone V 5CEBA4F23C7N (Terasic DE0-CV board)

Thankyou

JohnT_Intel
Employee
101 Views

Hi,

 

The external SDRAM is not initialize from the sof configuration. The external SDRAM need to be initialize by having the FPGA start to performed write into the SDRAM. May I know if you performed that in your design when it is power up or reset?

ABren1
Beginner
101 Views

​Thanks for the sof information (regarding limitations).

I have (i) mapped (thru BSP editor) external memory region + (ii) declaration of global variable and initialisation in C code in eclipse:

const unsigned char __atribute__ ((section ("bitmap.rodata"))) AB_X[2048] = { 0,124,...,0} //data is truncated for discussion purposes

 

I fully expected that the compiler/linker/HAL + boot loader would take care of the configuration of code/data.

So I was wrong on that front -> are you saying I have to load the data into ERAM myself using whatever means possible?

I could write it to Onchip memory temporarily and memcpy() it to ERAM if I have understood you correctly.

Thanks

JohnT_Intel
Employee
101 Views

Hi,

 

Yes, you can only initialize the Onchip memory and memory copy the data to the SDRAM. The reason is that the SOF file will only contain internal ERAM and there is no way to initialize it except that you memory copy it into the external ERAM.

 

ABren1
Beginner
101 Views

​Thanks JohnT,

Is this also the case for the .pof file programmed into the config device or does the .pof programmed EPCS provide loading of code & data space automatically

regardless of memory location? The reason I ask this is it appears that bootloaders can load into external RAM directly.

Unable to reply till Monday and once again Thanks JohnT

JohnT_Intel
Employee
101 Views

Hi,

If you are using POF file then whenever your system boot up, the bootloader will copy the data from the flash to the external RAM. This will be done automatically.

ABren1
Beginner
101 Views

​Ok and understand.

Thanks again.

A

ABren1
Beginner
101 Views

​Hi JohnT,

 Have programmed the ECPS64 with the .pof file generated and there is still no initialization of the external RAM. I tried using Convert Programming Files... option and including the SOF page and the HEX file of the external memory space that I want but it reported the following information box: "Data in Hex File overlaps between data blocks at address 10 and address 0" .When you then select "Generate" to generate the .pof file it says there is no input file. The next attempt I setup the compiler to generate a .pof file for the EPCS64 config device and the resultant file when programmed still doesn't have the external RAM that I have configured with the same values as in the initialization of my constant . Looking at the build tools progress: (I) A .hex file of the external RAM is never created, (ii) as stated previously the objdump file knows about my variable and memory space (iii) When I enable the alt_load() feature in the BSP editor, it doesn't copy the data I want to external memory from the .text region.

Can I attach an archive of the project to perhaps help you to better understand my problem space?

 

thanks,

A

Ahmed_H_Intel1
Employee
101 Views

Hi Andrew,

Yes please share with me the project if you want to understand the issue. BTW using the .pof or even the .jic is just a way to program memories with the targeted design files like .sof and .Hex

Anyway you must write to the SDRAM your data first. Please correct me if I understood the issue wrongly.

Regards,

 

ABren1
Beginner
101 Views

​Hi Embedded guy, belated thanks to your response. Couldn't (unable) share project but I have solved the problem. See below:

 

For interest I managed to solve this problem by creating a .hex file of the SDRAM contents I was hoping the compiler/linker would include in SDRAM initialisation during the turn on initialization process. bash -x 'elf2hex...

Then I added an EPCS Serial Flash Controller in the NIOS2 design in QSys, regenerated the System HDL and rebuilt the bsp & app. I programmed an empty spot in the EPCS64 config. device with the constant bitmap data contained in the .hex file mentioned above (Chose EPCS page 64 0x400000).

 

Then in C code opened a flash dev (using alt_flash_open_dev() ), read the flash info (using alt_get_flash_info() ), printed out info & config. to confirm device, then read the contents using alt_read_flash() and finally closed the flash device after read was completed (using alt_flash_close_dev() ). Just to confirm read in ok I did a memory dump out through the jtag uart to the nios2-terminal for the memory region of interest and confirmed it had the data I wanted stored.

Was some problems finding the EPCS device in the system.h file as it doesn't get added until you add it in QSys and regenerate the HDL.

Ahmed_H_Intel1
Employee
101 Views

Good to hear that. Sure you must include the device in Qsys and generate the HDL to get the required library in system.h

Regards.

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