Is it possible to use DDR3 without configuring it from the QSYS hardprocessor? I want to use DDR3 for the boot up of the HPS. What should be the steps i need to follow. Thanks.

[hsaee6]

I want to boot my HPS with out the FPGA support but using the DDR3.

How and where to configure the registers of the DDR3 if i dont want to use the configuration of the QSYS.

My HPS is connected to its own QSPI. and the FPGA is connected to the separate QSPI.

What should be the best BOOT mechanism for me?

boot from FPGA?

or

boot from QSPI connected to the HPS?

[HBhat2]

Hi,

As per my previous experience,

Although you are not using any logic in the FPGA, you have to use Quartus tool & Qsys. In the QSYS, configure the HPS with required IO muxing & boot source & HPS DDR3 configurations. Then just write a verilog/vhdl top module instantiatin the QSYS system.

Then compile the Quartus project & use the sopcinfo & FPGA binary for generating the HPS binaries like preloader, uboot etc. To generate HPS binaries, I think SOC EDS tool is used.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-a10-soc-boot.pdf - this document talks about HPS boot flow

With Regards,

HPB

[hsaee6]

Hello HPB,

Thanks for your reply.

it helped me allot.

now i have our own development board with DDR3 (MT41J128M16JT-125:K) and SoC (5CSEBA5U23I7N) on it.

i am now able to run the baremetal on chip memory by following this tutorial.

https://www.intel.com/content/www/us/en/programmable/documentation/lro1424280108409.html

Now i get the following error if i want to use "Create a New Scatter File to Locate the Bare Metal Application in the SDRAM"

ERROR(CMD16-TAD274-NAL22):

! Failed to load "bare metal-hello-world-01.axf"

! Failed to write 4,896 bytes to address S:0x02000000 while writing block of 4,096 bytes to address S:0x02000000

! General error on memory or register access.

Is there any method to debug why i get this error?

in my memory view of DS-5 i cant see the DDR3 memroy (my program runs in the endless loop)

Is there any possibility to move forward.

thanks.

:)

[HBhat2]

Hi,

Good to know that you are able to make the progress.!

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_bm.pdf

page 37

refer to "Create a New Scatter File to Locate the Bare Metal Application in the SDRAM " section

There are some similar errors mentioned and solution is mentioned. I think that should help you to proceed.

With Regards,

HPB

[hsaee6]

i forgot to mention in my question that,

I am getting this failure with and without the scatter file.

which address of the DDR3 memory should i use in my scatter file.

the scatter file which i am using is mentioned below.

SDRAM 0x02000000 0x02000000 ; 32M SDRAM

{

APP_CODE + 0

{

* (+RO , +RW , +ZI )

}

ARM_LIB_STACKHEAP 0x03000000 EMPTY 0x01000000 ; Application heap and stack

{ }

}

[HBhat2]

Hi ,

Sorry, I am not sure about DS5 flow as I never used it. But either in .sopcinfo file or device tree file SDRAM offset must be mentioned.

Any software engineer can help to solve this issues.

I would suggest you to post this issue under EDS group to get the answers

https://forums.intel.com/s/topic/0TO0P000000MWkdWAG/intel-soc-fpga-embedded-development-suite

With Regards,

HPB