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Altera_Forum
Honored Contributor I
943 Views

Is it possible to use the BeMicro SDK as a pure FPGA device?

Without the nios soft processor. Any tutotial or samples will be much appreciated. Thank you in advance.

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10 Replies
Altera_Forum
Honored Contributor I
93 Views

I don't know of any but to answer your question yes it is possible. The other devices on the board are embedded related but you should be able to access them using dedicated hardware instead of a CPU (might be difficult though...)

Altera_Forum
Honored Contributor I
93 Views

Thank you for the reply BadOmen! 

 

I'm a newbie to FPGA. When I made the purchase of the BeMicro I'm not that able to tell the difference between a soft-core processor and an FPGA integration module. It looks like I should have spent on the latter, and it will be a mission impossible for me at least for some years to turn the BeMicro into something I was looking for originally :rolleyes: 

 

To be honest the reason I got my hands on this device is mostly to explore and learn the parrallelism of FPGA, which originates from the hobby of data encryption - to speed things up. I'm not looking for hard-core code breaking (which from my understanding to do so it takes serious hardware and $$$ from a specific market), but just to learn and see how these things are done in principle. 

 

Wondered if i can still gain something out of the sitting stick :D 

 

Thank you again for the reply.
Altera_Forum
Honored Contributor I
93 Views

My guess is that the simplest way to do that is to use the processor to get a running system (slow but running). 

 

Then replace some parts of the code with "hardware accelerated IP" a.k.a., Nios custom instructions. 

 

And you can do it with the NIOS/E (the free one)
Altera_Forum
Honored Contributor I
93 Views

 

--- Quote Start ---  

Then replace some parts of the code with "hardware accelerated IP" a.k.a., Nios custom instructions. 

 

And you can do it with the NIOS/E (the free one) 

--- Quote End ---  

 

 

Thank you! Nios custom instructions? Does that mean these are APIs(?) that enable (or part of) source code to translate into FPGA, and somehow the Cyclone will be configured to fit? 

 

Sorry for my imprecise questions. My understanding is that the Cyclone on the SDK stick is configured to run an soft core processor/OS called Nios II, and on top of it we develop programs. This way we can benefit from the advantage of "future proofing" and transparency of the platform, which is one of the advantages FPGA offer. Programs developed this way can run on another hardware platform, and at the same time the Cyclone can be configured to run another soft-processor. 

 

However, another potential from FPGA is parallelism and speed advantages when the FPGAs are configured to run specific logic, which is what I'm looking for from the SDK stick. Is that "custom instructions" part going to help with custom/specific logic (like encryption/decryption)?  

 

Thank you in advance for any input.:-P
Altera_Forum
Honored Contributor I
93 Views

Ok I have do my homework. It is not the complete solution / sample I was looking for, but this thesis explained pretty clearly about the different componets like soft core processor, custom instructions, and c2h. I hope this will help if someone searched for similar stuff and came across this thread. 

 

http://www.imd.uni-rostock.de/veroeff/latex09_palma.pdf
Altera_Forum
Honored Contributor I
93 Views

You could leave Nios II out of the design and use the JTAG to Avalon bridge and system console instead. So you could fill up some memory with your input data using system console, kick off your accelerator hardware, then read back the results over system console to compare the results with known 'golden' results. (You won't be able to use C2H this way though since you need a Nios II core present).

Altera_Forum
Honored Contributor I
93 Views

Seriously, Isnt there a reference design for this board? A golden design? 

GOtta be kidding me..
Altera_Forum
Honored Contributor I
93 Views

 

--- Quote Start ---  

Seriously, Isnt there a reference design for this board? A golden design? 

GOtta be kidding me.. 

--- Quote End ---  

 

 

The 'golden design' is locked away. The Low-power DDR memory is not supported by Altera's IP core, its a third-party-IP core. Keep in mind that this is an Arrow design, not an Altera design, so Arrow was probably trying to promote its vendors. 

 

I just ignore the LPDDR. The 80-pin connector and the LPC-PROTO board (the board is known by lots of other names) is pretty useful for testing devices. 

 

Cheers, 

Dave
Altera_Forum
Honored Contributor I
93 Views

Well i made a design from scratch after some hours of research and it seems to be working. 

I downloaded the LPDDR IP from their vendor website and a license... hope it works well. 

I noticed there are tons of PORTS in the LPDDR, all i need for a linux design is PORT A and B, right? One for instruction and the other for DATA. 

 

Have you done anything with the LPDDR?
Altera_Forum
Honored Contributor I
93 Views

Hello microhk, 

 

I just read your question today. 

I started simply with an VHDL design in QuartusII, selected the device EP4CE22F17C7 (BeMicroSDK FPGA) for that project and used the built in programmer to download the generated (Compile) *.sof file to the BeMicro SDK stick. The BeMicro/USB-Blaster was recognized by the Programmer. 

Hope this is of any help to you or for others. 

 

Regards, 

benno
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