Is resetting eMMC device required in each power-on cycle of the HPS?

[Shahad]

I'm using Cyclone V [device: 5CSXFC6C6U23C7]

I want to use eMMC instead of the SDMMC device to store the Linux and FPGA binaries. Then boot the Linux and FPGA from the eMMC device.

My eMMC component has a reset input port. Is it required to reset the eMMC device in each HPS power-on cycle and when HPS assert cold or warm reset? is resetting the SDMMC controller is sufficient or we need to reset the SDMMC hardware as well?

My question comes from reading (section 4.2.1.8. For QSPI and SD/MMC/eMMC Provide Flash Memory Reset )

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an-cv-av-soc-ddg.pdf

[EBERLAZARE_I_Intel]

Hi,

Yes, the flash device is to be ensure that it is reset as well.

It is also documented on page 46 of that Device Design Guidelines.