Issues with Stratix IV E FPGA Dev Kit

[Altera_Forum]

We have a Stratix IV E FPGA Development Kit and recently started to use it. But we have several issues on the example designs included in the kit.  

 First, its example designs are segregated into several Quartus projects. That is, 'bts_ddr3' is for the DDR3 memory only, 'bts_hsmc' for the high-speed mezzanine card only, 'bts_qdr2' is for the QDR II+ memory only, 'bts_rldram' for the RLDRAM II only, and 'bts_config' for the rest (i.e. Ethernet, PIOs, LCD, and etc.). I am not sure why they are divided into separate projects besides saving a compilation time.   Second, the example designs are written in different languages. For instance, 'bts_ddr3' is in Verilog while 'bts_config' is in VHDL. Why in different languages? Anyway, the main problem is that we are used to designing with symbols in Quartus II Block Design File (.bdf), but the kit does not provide any .bdf files.  Third, when I restored the example designs delivered in a .qar file and compile it right way in Quartus II 9.1 without any changes, the TimeQuest Timing Analysis reports some critical warnings on hold and removal violations. I was expecting no timing violations. Am I supposed to have any violations? If I am, am I supposed to ignore such violations?  Fourth, I found this out in a hard way, but the 'bts_ddr3' example needs to be restored in the c:\altera\91\ip\altera\sopc_builder_ip\ to have it compiled correctly. Try to restore it in another path and regenerate its SOPC Builder for NIOS II and recompile in Quartus II, and you will have a few errors reporting some missing Verilog files during Analysis & Synthesis. If you don't regenerate the SOPC Builder, it won't produce any errors, though. My guess is that the DDR3 related file paths are defined as relative paths rather than absolute ones in the design.  If you have any comments to my issues, I would appreciate it if you can kindly reply to this post. Thank you for your time in advance.

[Altera_Forum]

Well I certainly don't have the kit but I'll give my insight: 

 First - This is not uncommon. They often provide several test projects that excercise different parts of the board. Why do they do this. I think it's because they don't know what aspect of the board a customer will be interested in. Usually the more exciting reference designs become available later (your board is pretty new). For example, you might shortly see a ethernet reference design or something like that.  Second - Yeah that's annoying. I haven't seen that before. Clearly they had different people working on example projects for the board.  Third - Are the timing warnings given of any real consequence? Even I choose to ignore some hold or removal warnings if I see them as having no real impact on the design.  Fourth - I'd have to see that one for myself. Most likely the library paths for the restored project need to be checked and set up properly.  Jake

[Altera_Forum]

Thank you for your reply, jacobjones. I especially appreciate it getting during the weekend.  

 I would like to answer your question about the timing problems. Since I am more like a software engineer, I had someone look into the TimeQuest report. He said he needs to understand the design to find out if they are critical or can be just ignored. That's a quite a problem because he has never seen the design, and the supplied example projects do not come with Quartus II Block Design Files (.bdf). As far as I know, there is no quick way to convert a VHDL or Verilog file into .bdf.

[Altera_Forum]

--- Quote Start ---  As far as I know, there is no quick way to convert a VHDL or Verilog file into .bdf.  --- Quote End ---   I think, there's no meaningful way to convert a behavioral HDL description into a schematic, at least without considerably reducing it's readability.

[Altera_Forum]

As a general note. I hope you have an FPGA designer to work with you.  

 Designing software for the NIOS is probably not much different than what you've grown accustomed to in designing software for other platforms. In addition, because the NIOS is FPGA based it gives you a ton of flexibility and power.  FPGA design on the other hand is very much non-trivial. Is it your intent to do the FPGA and software design yourself or will you be working with someone else?  Jake

[Altera_Forum]

jacobjones, I have four experienced FPGA designers working with me, and I am pretty much the only one software designer for NIOS II. They have been making very large, complicated FPGA designs many times, so they are pretyt good. But the problem is that all four FPGA designers have not used VHDL or Verilog extensively in the past.

[Altera_Forum]

Okay, as long as you've got some help.

[Altera_Forum]

--- Quote Start ---   ... Fourth, I found this out in a hard way, but the 'bts_ddr3' example needs to be restored in the c:\altera\91\ip\altera\sopc_builder_ip\ to have it compiled correctly. Try to restore it in another path and regenerate its SOPC Builder for NIOS II and recompile in Quartus II, and you will have a few errors reporting some missing Verilog files during Analysis & Synthesis. If you don't regenerate the SOPC Builder, it won't produce any errors, though. My guess is that the DDR3 related file paths are defined as relative paths rather than absolute ones in the design. ...  --- Quote End ---    Is the path mentionend above listed in SOPC Builder -> Tools -> Options? If not, maybe that's the problem...