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JIC file format - after "Examine" operation , why is "Signal Tap" written?

Amir3
New Contributor I
681 Views

Hello everyone,

 

In my system, from time to time some of the information in the Flash device goes wrong.


When I perform the "Examine" operation through the Programmer, I see that there is a difference between the original JIC and the extracted JIC from the Flash device, in the ASCII text section at the beginning of the files.

 

Note that Signal Tap Logic Analyzer was not enabled in this FW version.

 

what the meaning of this difference?

 

Original JIC file: "...Untitled..."

Amir3_0-1657782517017.png

 

Extracted JIC file: "...(V6AF7PBCE1LYS Signal Tap;)..."

Amir3_1-1657782627457.png

 

 

 

 

 

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FvM
Valued Contributor III
609 Views

Please notice that the .jic file header isn't read from the flash device rather than generated during programming file conversion respectively when storing the examined file. I don't know where the "Signaltap" text comes from, probably it has to do with the project loaded by Quartus at the time of examine operation. It doesn't tell anything about the .jic content.

 

Regards

Frank

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Farabi
Employee
663 Views

Hello Amir, 

 

From time to time the information of your flash device goes wrong, could you please elaborate more on that. 

Do the flash have issues during configuration? or when you try to program it?

 

regards,
Farabi

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Amir3
New Contributor I
658 Views

We store the configuration file (SOF/JIC) in MT25QL256 flash device from start address 0x0.

The FPGA in Active serial mode. 

 

Every ~500 power cycles, the system does not wake up, and after we program the flash device and restart the system, it goes back to work. We understand that we have a memory problem but we don't understand why.

 

To analyze the problem, we extract the data from the flash device by "Examine" operation.

 

We are trying to understand why it is written in the text of the extract file "...(V6AF7PBCE1LYS Signal Tap;)..." and not "...Untitled...".

By the way, if we do "Examine" to the system when the problem doesn't appear, we read in the extract file "...Untitled...".

 

 

 

   

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Farabi
Employee
614 Views

Hello,


Did you check the power rails to the flash device? or the signal integrity? if it can load/reload for 500 cycles, it should not caused by the flash contents.


regards,

Farabi


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FvM
Valued Contributor III
610 Views

Please notice that the .jic file header isn't read from the flash device rather than generated during programming file conversion respectively when storing the examined file. I don't know where the "Signaltap" text comes from, probably it has to do with the project loaded by Quartus at the time of examine operation. It doesn't tell anything about the .jic content.

 

Regards

Frank

Farabi
Employee
581 Views

Hi Amir,


Could you please check the signal or power rails using oscilloscope?


regards,

Farabi


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Farabi
Employee
539 Views

Hello,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


regards,

Farabi


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