JP0 and JP1 connection DEO nano board (Cyclone IV)
I have a question regarding the connections to a Cyclone IV FPGA mounted on the DEO nano board. I would like to connect 4 pins to the outside world: data_in, data_out, clk, and reset. In the assignment editor I have connected: clk - R8 reset - N9 data_out - R10 data_in - T10 My problem is: I can not find documentation that states all FPGA-IO with respect to the headers JP0 and JP1 (in terms of "R8.., N9..., R10, T10"). Am I doing something wrong? Thanks in advance,:) Eric edit :
The problem has been solved: in the attached documentation of the DEO nano-board I found the schematics of the board and the pin-connections of JP0 and JP1 to the FPGA.