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Altera_Forum
Honored Contributor I
743 Views

LED/Debouncing problems

Hello All, 

 

I am trying to test LED/debouncing logic for basic gates. Following is my code 

 

module ledtesting ( 

input clock, 

input A, 

input B, 

output C, 

output D, 

output E, 

output F 

); 

 

reg [60:0] count; 

wire slowclock; 

 

reg [3:0] debounce1; 

reg [3:0] debounce2; 

reg out1; 

reg out2; 

 

 

 

assign C = (out1 & out2); 

assign D = (out1 | out2); 

assign E = ~(out1 & out2); 

assign F = ~(out1 | out2); 

 

 

always @ (posedge slowclock) 

begin 

debounce1 <= debounce1 << 1; 

debounce1[0] <= A; 

out1 <= debounce1 == 4'hf ? 1'b1 : 1'b0; 

debounce2 <= debounce2 << 1; 

debounce2[0] <= B; 

out2 <= debounce2 == 4'hf ? 1'b1 : 1'b0; 

 

end 

 

 

always @(posedge clock) 

count = count + 1'b1; 

 

assign slowclock = count[24]; 

 

endmodule 

 

 

The problem is that my leds (C, D, E, F) are not functioning correctly. Basically AND, OR logic are switched, NAND, NOR logic are switched. Can anybody tell me what might be the problem. I copied this code from a website, could reset be the problem? The pin assignment is correct, i have checked it about 10-15 times. 

 

Thanks a bunch for your help 

NEO
0 Kudos
9 Replies
Altera_Forum
Honored Contributor I
44 Views

Is the input clock OK? What is the frequency? Remember that slowclock which drives the debounce is very much slower than the input clock so if you have a an input clock of a few KHz you may need to wait many seconds for a result!

Altera_Forum
Honored Contributor I
44 Views

The Input clock is the clock of MAX II CPLD i.e 66 MHz. I did a counter example on the LEDs and it works fine, so there is nothing wrong with the pin assignment, something should be wrong with the logic of my debouncing example or the reset. Any ideas on how to debug this. 

 

Thanks, 

Vinay
Altera_Forum
Honored Contributor I
44 Views

try this: 

 

always @ (posedge slowclock) begin debounce1 <= debounce1; debounce1 <= A; out1 <= debounce1 == 4'hf ? 1'b1 : 1'b0; debounce2 <= debounce2; debounce2 <= B; out2 <= debounce2 == 4'hf ? 1'b1 : 1'b0; end
Altera_Forum
Honored Contributor I
44 Views

Tried it, did not work!!

Altera_Forum
Honored Contributor I
44 Views

I am not sure what you mean by "not work". 

are leds off on all outputs, can describe each output. 

 

Your inputs A,B must stay high for very long time for debounc1 or debounce2 registers to become f, otherwise out1,out2 will stay zero always
Altera_Forum
Honored Contributor I
44 Views

Sorry for not being clear, 

 

When i press one of the push buttons for a good amount of time (enough time to be debounced),  

led1 (which is suppossed to work as an and gate) lights on instead of led2 

similarly led3 (supposed to work as a NAND gate) lights off instead of led4 being off. 

 

When i press both the push-buttons led1 and led2 turns on and led3 and led4 turns off (which is correct behaviour). Thus it seems like AND,OR logic are switched, NAND,NOR logic are switched as seen on the LEDs. The push-buttons have been pressed for a good amount of time so that i can see some effect on the leds.
Altera_Forum
Honored Contributor I
44 Views

OK understood now. you mean: 

any one button pressed => AND/OR/NAND/NOR work opposite 

two buttons pressed => all work 

 

Sounds difficult now, is your timing ok. I know it is slow clk but you shouldn't ave timing problems. Is your slow clk made global. 

I suggest you make cnt(24) enable, thus use fast clk on the process but add: 

if cnt(24) = '1' then.... 

 

instead of using cnt(24) as clk. 

 

edit: you need to make cnt(24) as one clk pulse
Altera_Forum
Honored Contributor I
44 Views

please correct syntax(I am vhdl poisoned) 

always @ (posedge clk) 

begin 

slow_clk_d <= slow_clk; 

if(slow_clk == '1' and slow_clk_d == '0') 

debounce1[3:1] <= debounce1[2:0]; 

debounce1[0] <= A; 

out1 <= debounce1 == 4'hf ? 1'b1 : 1'b0; 

debounce2[3:1] <= debounce2[2:0]; 

debounce2[0] <= B; 

out2 <= debounce2 == 4'hf ? 1'b1 : 1'b0; 

 

end 

end
Altera_Forum
Honored Contributor I
44 Views

Hey Kaz, 

 

Thanks for your help in debugging the issue. It was actually a simple bug in my design. The push-buttons and the leds are at active low, while the logic i am trying to implement is active high so i had to convert the signals from debounce to active high, do my basic gates and then convert to active low to output at the leds. Thus i changed my code to 

 

lways @ (posedge slowclock) 

begin 

debounce1[3:1] = debounce1[2:0]; 

debounce1[0] = A; 

out1 = debounce1 == 4'h0 ? 1'b1 : 1'b0; 

debounce2[3:1] = debounce2[2:0]; 

debounce2[0] = B; 

out2 = debounce2 == 4'h0 ? 1'b1 : 1'b0; 

end 

 

assign C_c = (out1 & out2); 

assign D_c = (out1 | out2); 

assign E_c = ~(out1 & out2); 

assign F_c = ~(out1 | out2); 

 

assign C = ~C_c; 

assign D = ~D_c; 

assign E = ~E_c; 

assign F = ~F_c;  

 

 

and it worked. Thanks a ton for your help in debugging my issue. 

 

-Vinay