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LLE 10G MAC + 1G/2.5G/5G/10G Multi-rate Ethernet PHY




I am implementing example designs generated through Example Design Tab - 

LLE 10G MAC + 1G/2.5G/5G/10G Multi-rate Ethernet PHY

on Arria 10 FPGA and testing it on a custom development board which has some clock limitation and can only generate 322.265625 MHz and 100 MHz clocks. With several approaches to use IOPLL and ATX PLL to generate 644.53125 MHz and 125 MHz clocks and failed to fit the design,


I moved to LLE 10G MAC + 10G BASE-R PHY which uses 322.265625 MHz as ref_clk. Now I am using IOPLL only to generate 125MHz csr_clock (with Global_Clock assignment). As I am running the tcl scripts (gen_conf.tcl) on system console I am observing the following errors - 


error: master_read_32: This transaction did not complete in 60 seconds. System Console is giving up.
while executing
"master_read_32 $jtag_master $address_hex 1"
(procedure "rd32" line 6)
invoked from within
"rd32 0x0 0x100 0x00"


Any input/information to solve this would be greatly appreciated.


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