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LVDS receiver PLL

jerry_anto
Beginner
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For the requirement of our project, we wanted to use 3 lvds receivers, each for one video in. 
 
jerry_anto_1-1692947339319.jpeg

 

Unfortunately since each lvds receiver uses one pll, the pll usage increases. We are using one pll for mipi (MIPI PLL) and one for generating transceiver clock (PLL 50)  .
The issue with using these 5 PLLs is one of my LVDS_RX and MIPI PLL are in the same bank (4A), the chip planner is trying to place both in the same location. ( X68 Y0) approx. 
 
We tried several ways to use a single pll for all 3 lvds_rx but it didn't work.
 
  1) use external PLL using the Mega-wizard.
  2) Using alt clk ctrl IP
 
It would be really helpful if we get a solution to use one pll for all the lvds receivers.
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AqidAyman_Intel
Employee
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Hello,


When you tried the external PLL, have you followed this guideline in below link?

https://www.intel.com/content/www/us/en/docs/programmable/683375/current/lvds-interface-with-external-pll-mode.html


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AqidAyman_Intel
Employee
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As we do not receive any response from you on the previous question/reply/answer that we have provided, please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.



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