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Honored Contributor I
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LVDS receiver resistors

I'm currently developing on a DE2-115 together with an HSMC daughter card (TI's ADS58B18EVM through HSMC-ADC-bridge adapter). I need to use LVDS I/O standard for interfacing the cards, so I know I have to install 100-ohm resistors close to the FPGA to get things working. 

 

I've looked on the web for a DE2-115 BOM or layout to find resistors part number or at least physical dimensions, but I couldn't. 

 

Where can I find the informations I need? Anyone can help? 

 

Thanks in advance. 

 

Regards, 

Lorenzo
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Honored Contributor I
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Use 0402 or 0603 chips (or even 0201), whatever fits your layout.

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Honored Contributor I
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Hi Lorenzo, 

 

--- Quote Start ---  

I'm currently developing on a DE2-115 together with an HSMC daughter card (TI's ADS58B18EVM through HSMC-ADC-bridge adapter). I need to use LVDS I/O standard for interfacing the cards, so I know I have to install 100-ohm resistors close to the FPGA to get things working. 

 

I've looked on the web for a DE2-115 BOM or layout to find resistors part number or at least physical dimensions, but I couldn't. 

 

Where can I find the informations I need? Anyone can help? 

 

--- Quote End ---  

I just looked for the layout in the DE115 distribution, but they only have the schematic in there. Page 23 shows the termination resistors you need to load on the DE115. 

 

Try and locate R55, R56, etc. The footprints are most likely 0402 (40 mils x 20 mils = 1 mm x 0.5 mm). If the pads on the resistor footprints are about the same distance apart as the BGA balls (or the vias on the bottom of the PCB ), then the resistors are 0402. 

 

If you cannot figure it out, let me know, and I'll look on the board I have at home. 

 

Cheers, 

Dave
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Honored Contributor I
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Hi Dave (don't know if you remember, but you've already helped me once). 

 

I'm currently checking what you said: comparing Cyclone IV BGA with resistors length, it seems like they're 0402. Anyway, I haven't got much experience with this kind of stuff, so I wouldn't put the hand on fire. 

 

If you could check for me I would be very grateful. If you have no time no problem, I'll try with 0402. 

 

Anyway thanks for your still precious help! 

 

Cheers, 

Lorenzo
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Honored Contributor I
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Hi Lorenzo, 

 

--- Quote Start ---  

 

I'm currently checking what you said: comparing Cyclone IV BGA with resistors length, it seems like they're 0402. 

 

--- Quote End ---  

 

 

Do you have some 0402 resistors to install? 

 

 

--- Quote Start ---  

 

If you could check for me I would be very grateful. If you have no time no problem, I'll try with 0402. 

 

--- Quote End ---  

 

 

I'll have a look tonight when I go home.  

 

If you want a faster double-check, you could post a photo where you can see the resistors and the BGA balls. 

 

Cheers, 

Dave
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Honored Contributor I
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No, I don't have 0402 resistors, I would order them. I was just trying to make a guess by eye comparing BGA balls distance with resistors footprint on the board, that's why I'm not sure. 

 

Anyway I don't hurry, so if it isn't a problem for you I'll wait for your check. 

 

Thanks again Dave. 

 

Cheers, 

Lorenzo
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Honored Contributor I
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--- Quote Start ---  

 

Anyway I don't hurry, so if it isn't a problem for you I'll wait for your check. 

 

--- Quote End ---  

 

Ok, I'll look tonight. 

 

Cheers, 

Dave
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Honored Contributor I
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The LVDS termination resistors are located on the top-side of the DE115 PCB between the FPGA and the GPIO/HSMC connectors. They are 0402 packages. 

 

On the board I have, the resistor pads have solder blobs on them. Before you try to solder resistors, remove the blob from one side of the resistor using solder wick. Leave the other blob there, you can use that when tacking the resistors to the board. You can hand-solder the resistors easy enough. Either use head-mounted magnifying glasses or a microscope. 

 

Make sure you have spare resistors, they're pretty hard to find when you drop them :) 

 

Cheers, 

Dave
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Honored Contributor I
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Great! That helps more than I needed. I don't know how I would do without your support! :) 

 

Thank you so much Dave and talk to you soon. 

 

Cheers, 

Lorenzo
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Honored Contributor I
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I'm currently developing on a ArriaII EVM together with an HSMC daughter card (TI's ADS62p29EVM through HSMC-ADC-bridge adapter).(that's very similar to your design) I also need to use DDR LVDS for interfacing the cards. 

But I'm a freshman with this interface and are confused about DDR LVDS. I want to see the actual waveform using signaltapII. 

I added a DDRIO_in megafunction to interfacing the ADC chip.Pin IN[5:0] and INCLK are from ADS62P29 and SIGNAL_TAP_CLK is used in the signaltap clk. 

But it can't compile successfully.I got an fitter error:Folling 6 routing resources needed by more than one signal during the last fitting attempt.The 6 pins are IN[5:0]. 

Do I miss something like sdc or regenerator the INCLK in the PLL module, I really don't know how to find this informations. 

Many thx. 

Regards, 

Alan
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Honored Contributor I
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--- Quote Start ---  

 

I added a DDRIO_in megafunction to interfacing the ADC chip.Pin IN[5:0] and INCLK are from ADS62P29 and SIGNAL_TAP_CLK is used in the signaltap clk. 

 

--- Quote End ---  

 

 

You cannot probe at the DDR inputs, you need to probe at the DDR block outputs, i.e., the half clock-rate data. 

 

Cheers, 

Dave
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Honored Contributor I
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Hi smileface, I'm sorry but I don't know how to help you. I haven't got the interfacing to ADC done until now because I've still got problems with the hardware to work on. 

 

Anyway, I think there is nothing much to know about DDR LVDS: the first word means that bits are alternatively sent on each edge of the clock (for my ADS58B18, as it is found on its datasheet, odd bits of each sample are sent on the rising edge of the clock, even bits on the falling one); the second word means that 0 and 1 logic levels are defined with respect to the voltage difference among two pins of the FPGA (which anyway have to support this kind of I/O standard, as it is the case for FPGA pins connected to HSMC connector on my board). So, each of the two things can exist without the other. 

 

I don't know if this is the right choice, but I've tried to implement "manually" the shifting of the input bits in a register (without using the IP you mentioned) and I'm currently simulating my design. If you want, I'll let you know if it works once programmed on the FPGA. 

 

Please some guru correct me if I'm wrong with anything I've said, as this could be of help for me too. 

 

Regards, 

Lorenzo
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Honored Contributor I
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Hi,Lorenzo, 

Thank you for your reply. 

 

The interface of ADS58B18 is very similar with the ADS62P29 which also supported DDR LVDS or CMOS level. 

 

why not use altlvds_rx or altddio ? 

Did you try to use two register to acquire data triggered by the rising and falling edge and then shift the bits to a register. (integrate the odd and even bit)  

 

Do you use the PLL with the clkout_p and clkout_n from the ADS58B18. 

best regards 

 

Alan
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Honored Contributor I
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Hi Alan, 

as I previously said I couldn't verify my firmware yet because of some problems with the hardware, so I can't tell you that my solution works.  

 

Anyway, my point of view is not to use any IP untill you really need it, and since the problem seemed easy to understand and solve for me I tried to do it in VHDL. I still haven't used any PLL for the implementation of that interface, even if I think I will probably have to. 

 

So my answer is: let me try if my solution works and I'll let you know how I did it =) 

 

Regards, 

Lorenzo
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Honored Contributor I
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Hi smileface, 

 

I finally switched to use altddio IP (I'm not sure altlvds_rx fits our needs). I'm still having some problems in getting the right interpretation of what I'm receiving, but at least the devices seem to communicate with each other.  

I think that, at the frequency we're dealing with, I/O timing should be important. The following link explains well source-synchronous interfaces: there's also an application example with an ADC from TI in all similar to ours. 

 

http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest 

 

Regards, 

Lorenzo
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