FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5197 Discussions

Line_VALID timing from D5M camera

Altera_Forum
Honored Contributor II
830 Views

Hi guys, 

 

I am using the demo code of D5M on DE2-115. And I didn't change the camera settings in I2C_CCD_Config, in which Width = 800, HBMIN(horizontal blank) = 500, PIXLCLK = 50MHz. 

 

So the length of Line_VALID signal should be 800 + 500*2 = 1800, correct? 

 

But when I monitored the signal of Line_VALID,I found that: 

time Line_VALID = 1 is 16 us, which equals 800 pixels. This is meaningful 

but time Line_VALID = 0 is about 31.1 us, which equals around 1555. But I though it should be 2*HBMIN = 1000.  

 

Can you tell me which part is wrong? Thanks very much! 

 

 

BTW: The default settings for D5M camera are: 

 

EXTCLK (MHz) 50 

Col_Bin 1 

Row_Bin 1 

Col_Skip 1 

Row_Skip 1 

Col_Size 1599 

Row_Size 1199 

Shutter Width (SW) 1984 

Horizontal Blanking 0 

Vertical Blanking 25
0 Kudos
0 Replies
Reply