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Hi,
I'm trying to use the Megawizard memory compiler in the Linux 9.1 beta to create a simple dual port ram with one read port and one write port. As soon as I click the radio button that says "One read port and one write port (simple dual-port mode)", the write data input on the RAM symbol to the left disappears. If I go all the way through the wizard and generate the Verilog file for the RAM, sure enough, it is missing its write data input.Link Copied
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yes, i can confirm this behavioral.
it is true and seems to be a bug also i am not asked if i would like to have VHDL or verilog HDL output files, the wizzard generates VHDL could you please fill out a service request for MySupport on the altera web page ?- Mark as New
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Service request submitted,# 10742640
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