- I have configured from Platform Designer the Peripheral pins of HPS, set UART to "Unused" and Mux Table to Loan uart0_rx and uart0_tx .
- Exported those pins to the HPS module and connected them in the top level HPS instantiation.
- Synthesis will report: Error (35030): Partition "soc_system_hps_0_hps_io_border:border" contains I/O cells that do not connect to top-level pins or have illegal connectivity.
- From there I'm blocked.
- I have followed Section 4 of Intel's application note ftp://ftp.intel.com.br/Pub/fpgaup/pub/Intel_Material/16.1/Tutorials/Accessing_HPS_Devices_from_FPGA.pdf
Further advise is much appreciated.
Here I found good information:
using IoLoan 49 and 50 and setting HPS_UART_RX and TX to bidir, the project got synthesized.
No time to deal with quartus_hps.exe for QSPI programming for HPS
Have you look through here? Not sure if it might help:
The topic discussed on utilization unused HPS IOs as LoanIO, and directly driven by the FPGA thus it can be used as input, output, or bi-directional IO.
Is this issue same as your previous post? I noticed the you have made 2 posts regarding Loan IO.
Hi, thanks for the reply.
Yes, in the rush of solving issue I re-asked about the topic.
Key was to use loanio pins 49 and 50, and not 60 and 61 as one may infer fro Platform Designer at first sight (Likely the extreme reduced size of the GUI in 4k screen added more difficulties to the proper setup). This can be confirmed in DS1 board schematic or the pin planner (pins B25 and C25 are mapped to io 49 and 50)
As for the connection here the information which brought clarity for me:
It was also mandatory to:
- define the HPS_UART_RX and TX ports as inout in the top level, otherwise synthesis will fail
- to program preloader with the hps configuration. (I need to confirm whether u-boot was also a requirement in the SD card as well). Its worth mentioning that rev G of the board has removed the programming select switch, so no QSPI interface available, SD card is simplest approach.
Finally I'm getting the UART properly interfacing HOST<->FPGA in CycloneV
From brand new board box to working system it took likely 40 man hours for experienced FPGA engineer.