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Altera_Forum
Honored Contributor I
784 Views

Looking for a design for the Cyclone III FPGA Development Board with MMU

I'm looking for a recent design for the cyclone iii fpga development board using a Nios2 with MMU and the TSE. 

I am using QII 10.1sp1 and SOPC Builder. 

 

Are there some as 'reference design' ? 

 

TIA, 

Fred
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5 Replies
Altera_Forum
Honored Contributor I
55 Views

Finally, I found one here (http://www.alterawiki.com/uploads/f/f6/20110211_nios2_linux_3c120_125mhz_10.1sp1.tgz). 

However, I can't compile it, using QII v10.1sp1, without a 'Timing requirements not met'...
Altera_Forum
Honored Contributor I
55 Views

Check what timing requirements it fails... Possibly JTAG or something not very serious.

Altera_Forum
Honored Contributor I
55 Views

The Worst case Timing Paths indicates a slack=-0.033 for the Slow 1200mV 85C Model Setup of the ddr2_Lo_xxx|altpll_component|...pll1|clk[1]. 

 

I don't know if there is a relationship, but the verification fails after a nios2-download of my kernel...
Altera_Forum
Honored Contributor I
55 Views

And the same problem is reported also in the Worst-case slack section of "Multicorner Timing analysis Summary".

Altera_Forum
Honored Contributor I
55 Views

Finally, my kernel boots, it was a bad software configuration. It hangs a little bit later, but that's normal life for a first try! 

 

I hope/suppose the Timing error is not too serious...
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