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I am attempting to use the Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Core on the Stratix 10 Transceiver Signal Integrity Kit but am unable to communicate with the board. I am using a Mellanox MMA1B00-C100D optical module in the QSFP0 cage on the board and am looking at the transmit pins of the module for light but not seeing any. I am able to see light when I program the board with the qts_qsfp_sfp binary from the board support zip. When I instantiate the Low Latency 100G MAC from the qts_qsfp_sfp project I also do not see light from the optical module.
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- Intel® Stratix®
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Hi Sir,
For the LL 100G Ethernet IP design example, you can refer to the following link to create/generate it for the S10 Transceiver SI kit.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-s10-ll-100gbe.pdf
To isolate the problem, please try to turns on internal serial loopback and see if it can transmit and receive packet? Besides, if possible, please use a QSFP loopback module to perform the loopback.
Regards -SK

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