MAX II PCI Development Kit

[Altera_Forum]

Hello, I am having some problems getting started. I am new to Altera and PCI... I loaded the PCI example and tried to compile and get a ton of errors. I also tried to follow the directions for using SOPC builder, but it doesn't match the software that I am using. I have the latest Web version 9.1. I am getting these errors when compiling: Info: ******************************************************************* Info: Running Quartus II Analysis & Synthesis Info: Version 9.1 Build 222 10/21/2009 SJ Web Edition Info: Processing started: Mon Dec 14 10:25:14 2009 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off top_pci32 -c top_pci32 Info: Found 1 design units, including 1 entities, in source file lcd_cntrl.v Info: Found entity 1: lcd_cntrl Info: Found 1 design units, including 1 entities, in source file mem_cntrl.v Info: Found entity 1: mem_cntrl Info: Found 1 design units, including 1 entities, in source file perip.v Info: Found entity 1: perip Info: Found 1 design units, including 1 entities, in source file temp_cntrl.v Info: Found entity 1: temp_cntrl Info: Found 1 design units, including 1 entities, in source file top_local.v Info: Found entity 1: top_local Warning: Can't analyze file -- file ../../../../../MAX_II_Dev_kit-v6.0.1/Examples/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/t32.v is missing Warning (10463): Verilog HDL Declaration warning at top_pci32.v(151): "local" is SystemVerilog-2005 keyword Warning: Using design file top_pci32.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: top_pci32 Warning (10236): Verilog HDL Implicit Net warning at top_pci32.v(116): created implicit net for "lt_rdyn" Warning (10236): Verilog HDL Implicit Net warning at top_pci32.v(117): created implicit net for "lt_abortn" Warning (10236): Verilog HDL Implicit Net warning at top_pci32.v(118): created implicit net for "lt_discn" Warning (10236): Verilog HDL Implicit Net warning at top_pci32.v(119): created implicit net for "lirqn" Warning (10236): Verilog HDL Implicit Net warning at top_pci32.v(123): created implicit net for "sram_ce2" Warning (10236): Verilog HDL Implicit Net warning at top_pci32.v(142): created implicit net for "lt_framen" Warning (10236): Verilog HDL Implicit Net warning at top_pci32.v(143): created implicit net for "lt_ackn" Warning (10236): Verilog HDL Implicit Net warning at top_pci32.v(144): created implicit net for "lt_dxfrn" Info: Elaborating entity "top_pci32" for the top level hierarchy Info: Elaborating entity "top_local" for hierarchy "top_local:local" Info: Elaborating entity "mem_cntrl" for hierarchy "top_local:local|mem_cntrl:mem_cntrl" Info: Elaborating entity "perip" for hierarchy "top_local:local|perip:perip" Info: Elaborating entity "lcd_cntrl" for hierarchy "top_local:local|perip:perip|lcd_cntrl:lcd" Info: Elaborating entity "temp_cntrl" for hierarchy "top_local:local|perip:perip|temp_cntrl:temp" Warning (10036): Verilog HDL or VHDL warning at temp_cntrl.v(55): object "cntrl" assigned a value but never read Warning: Using design file t32.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info: Found entity 1: t32 Info: Elaborating entity "t32" for hierarchy "t32:core" Error: Node instance "pci_t32_inst" instantiates undefined entity "pci_t32" Info: Generated suppressed messages file C:/altera/Kits/MAXII_1270N_Kit-v6.0.1/Examples/ReferenceDesigns/PCI_ReferenceDesign/QuartusProject/top_pci32.map.smsg Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 13 warnings Error: Peak virtual memory: 159 megabytes Error: Processing ended: Mon Dec 14 10:25:15 2009 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 Error: Quartus II Full Compilation was unsuccessful. 3 errors, 13 warnings Can someone please help with what any of this means? Thanks

[Altera_Forum]

You'd better classify the err logs, or it really seems messed up...