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MAX V器件内部振荡器产生的时钟能否作为CPLD逻辑侧的全局时钟使用

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YuanLi_S_Intel
Employee
‎02-26-2020 02:08 AM
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你是说clock共应，可以用在MAX V内部​逻辑侧吗？是可以的

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