MAX V CPLD Development Kit

[Moe1]

MAX V CPLD Development Kit - Will not work for a simple logic circuit

Intel Community, I recently purchased the Max V Development Kit. I figured out how to use the Quartus Prime Lite and successfully installed the Blaster. Created a simple encoder logic circuit, two inputs, one as a 0 or 1 input and the other an enable input. The circuit comprises of two 'AND' gates and on 'NOT' gate. When the first input is low the first AND gate input is low and the other AND input is high because of the NOT gate. The second input is an enabling input which allow the true states of the AND gates to be outputted else the outputs are always low when the enable input is low. Successfully created this logic, manually assigned pins, compiled and synthesized, etc. Successfully downloaded to the Max V kit. Wired up to test the CPLD, nothing. Absolutely nothing. I am not sure how to wire the board for the inputs to be applied. I assigned J6.1 as input, J6.2 as enable input. Pins J6.5 and J6.6 are the two AND gate outputs. Also, I accepted the 3.3 LV default. When I test with external switches to the board and outputs to a O-scope, nothing, and sometimes erratic outputs that make no sense. I have searched for many weeks any examples on interfacing external inputs devices and output devices to the board and have not found any thing. Is there any help to be found in the Intel Community?  Are there any learning material available specific to the MAX V development board?  Any written books?  Thank you. My email is : moejjunior@gmail.com

Please note that I originally posted this sometime back but I had to travel and now I am back and  no better results.  Frustrating.

I really need HELP.

Thank you.

[Moe1]

Intel Community, I recently purchased the Max V Development Kit. I figured out how to use the Quartus Prime Lite and successfully installed the Blaster. Created a simple encoder logic circuit, two inputs, one as a 0 or 1 input and the other an enable input. The circuit comprises of two 'AND' gates and on 'NOT' gate. When the first input is low the first AND gate input is low and the other AND input is high because of the NOT gate. The second input is an enabling input which allow the true states of the AND gates to be outputted else the outputs are always low when the enable input is low. Successfully created this logic, manually assigned pins, compiled and synthesized, etc. Successfully downloaded to the Max V kit. Wired up to test the CPLD, nothing. Absolutely nothing. I am not sure how to wire the board for the inputs to be applied. I assigned J6.1 as input, J6.2 as enable input. Pins J6.5 and J6.6 are the two AND gate outputs. Also, I accepted the 3.3 LV default. When I test with external switches to the board and outputs to a O-scope, nothing, and sometimes erratic outputs that make no sense. I have searched for many weeks any examples on interfacing external inputs devices and output devices to the board and have not found any thing. Is there any help to be found in the Intel Community?  Are there any learning material available specific to the MAX V development board?  Any written books?  Thank you. My email is : moejjunior@gmail.com

Please note that I originally posted this sometime back but I had to travel and now I am back and  no better results.  Frustrating.

I really need HELP.

Thank you.

[EngWei_O_Intel]

Hi there

I check the pin usage of those 4 pins in the pinout list and they look fine. 

There is a complete kits here which include examples with source file in the  "examples" folder.

thanks.

Eng Wei

[Moe1]

EngWei_O_Intel,

Where is the examples source files located?

Also, today I was told that the MAX V CPLD Development Kit is not a CPLD.  This is confusing to me when everything on the box, etc., states ...CPLD... kit.

Thank you.

[Moe1]

EngWei_O_Intel,

I forgot another question.

How about my understanding of the J6.29 > VCCin and J6.30 > Gnd pins?  Since right now I am not doing any logic level shifting between logic levels I am inputting 3.3 VDC from an external power source to drive external 3.3 VDC device.

Thank you.

[EngWei_O_Intel]

Sorry for missing to attach the link:

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-max-v.html

This is the path where the example located on:

<installation_path>\kits\maxV_5m570z_cpld\examples\golden_top

The schematic is located here:

<installation_path>\kits\maxV_5m570z_cpld\board_design_files\maxv_5m570z_dev\schematic

The userguide in the above link shall explain the connector's connection. 

Base on the mapping of the pin name, you can also refer to the requirement of each pin here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/max-v/pcg-01012.pdf  (pin connection guideline) 

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html (pinout file)

Thanks.

Eng Wei

[Moe1]

EngWei_O_Intel,

I am still getting the same results.  I will create a video showing from start to finish what's being done.

Will take a few days to create.  This will show exactly what's being done and what's happening.

, Morris Jr.