FPGA, SoC, And CPLD Boards And Kits
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MAX V DK Bugs

Altera_Forum
Honored Contributor II
‎08-17-2012 01:07 PM
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I have a MAXV Dev Kit and there are errors in the documentation. Referring to the "MAX V CPLD Development Board Reference Manual", Table 2-9 on Page 2-9.  

 

Jumper 7.2 = D16 (not C14) 

Jumper 7.3 = C14 (not D16) 

 

Jumper 7.6 = B14 (not D13) 

Jumper 7.7 = D13 (not B14) 

 

I would report this on the Altera site but I cant find a link for such inputs. Perhaps a mod can pass this onto the relevant person.
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Altera_Forum
Honored Contributor II
‎08-17-2012 02:11 PM
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Raise a request via mysupport 

https://www.altera.com/myaltera/mal-index.jsp
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