FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

MAX V DK Bugs

Altera_Forum
Honored Contributor II
821 Views

I have a MAXV Dev Kit and there are errors in the documentation. Referring to the "MAX V CPLD Development Board Reference Manual", Table 2-9 on Page 2-9.  

 

Jumper 7.2 = D16 (not C14) 

Jumper 7.3 = C14 (not D16) 

 

Jumper 7.6 = B14 (not D13) 

Jumper 7.7 = D13 (not B14) 

 

I would report this on the Altera site but I cant find a link for such inputs. Perhaps a mod can pass this onto the relevant person.
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
100 Views

Raise a request via mysupport 

https://www.altera.com/myaltera/mal-index.jsp
Reply