MAX10(10M50DAF484C8G): VCCIO voltage change (from 3.3V to 1.8V) in Runtime

[Pooja_03]

Hi,

What will happen if few bank of MAX10 will get power delayed by few seconds w.r.t to other MAX10 supplies? 

Can we change MAX10 VCCIO voltage in runtime? 

Thank you

[Pooja_03]

Hi,

Gentle reminder!

Thank you

[FvM]

Hi,
MAX10 VCCIO bank 1 and 8 are monitored by POR circuit and prevent device configuration if not powered.

Other VCCIO bank supplies are not monitored. MAX10 datasheet specifies however:

"VCCIO for all I/O banks must be powered up during user mode because VCCIO I/O banks are used for the ADC and I/O functionalities."

Obviously this doesn't answer your question "what will happen if". My guess is that it won't damage the FPGA. Ramping VCCIO within legal VCCIO levels (1.2 to 3.3 V) should be also possible as long as maximum pin currents are observed.

[AqidAyman_Intel]

Hello,

I wish to follow up with you, since the reply provided, do you need more support or clarification on this question before I close this thread?

Regards.

Aqid

[Pooja_03]

Hi Aqid,

Thank you for your response. 

It is cleared. You may close this thread.

Thank you

[AqidAyman_Intel]

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