FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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MAX10 Evaluation Kit Mechanical Locations of Connectors

Honored Contributor II

Dear All, 


I am designing a daugtherboard for the MAX10 EVK (EK-10M08E144ES/P) to test a proof-of-concept. To do so, I need the physical locations of Pin 1 of the 8-pin headers (J2, J3, J4, J5) the the unpopulated 40-pin headers (J8, J9). 


I have seen the design package for the EVK that includes a Cadence .brd file which would have the required information. Unfortunately, as an Altium user, I cannot import the file to obtain the dimensions - I would need the Allegro ASCII .alg file instead. Alternatively, a simple dimensioned drawing in PDF (or similar) would work well. 


Is there a location in the documation that has this information that I have missed? 


-- Damien
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Honored Contributor II

I believe you might want to try to contact Altera to request for the different file format than what is provided with the design package.

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