MAX10 FPGA develop kit download data from DDR3 through Triple speed ethernet IP

[wuhannus]

Hi who may concern,

Recently we have used the MAX10 FPGA develop kit (Manufacture No: DK-DEV-10M50-A) to store the data on the board DDR3 memory which is around 1.5Gb. Now we are trying to download the data from the DDR3 SDRAM to our PC using the triple speed ethernet(TSE) IP. We searched on website, the example will always use the NIOS II to generate the Micro system (As shown in the below link) to operate the TSE IP.

https://fpgacloud.intel.com/devstore/platform/15.1.0/Standard/max-10-single-port-triple-speed-ethernet-and-on-board-phy-chip-design-example/

However, we do not have the IP license of nios II system for TSE qsys. I have the following two questions.

1. Is there anyway that we can instantiate the TSE IP just as the same way we instantiate the DDR3 controller IP without license limitation? Directly using the verilog code can let us have a clear data flow path to moving the data.  If it is possible, is there any example on the website for us to follow up. The ethernet IP documentation looks much more complex than DDR3 IP. 

2. We also tried to use UART IP, it is qsys ip which still needs the license. Is there any example on the website of the MAX10 board UART operation using without license limitation? 

Thanks very much for your help.

[AR_A_Intel]

Hello

Welcome to INTEL forum. Based on my understanding, for now we don’t have full system reference design that you are looking. We only have individual IP example design that’s generated from IP solution directly. For instance, DDR3 example design generated from DDR3 IP, TSE example design generated from TSE IP

[wuhannus]

Hi Rahman,

Thanks for the information.

Form my experience with DDR3 IP, it can be instantiated directly in MAX10 FPGA develop kit without license requirement.

However, the TSE IP instantiation can only from qsys file and need the license requirement. From your opinion, is there any way to instantiate the TSE IP without license requirement?

 Thanks.

[AR_A_Intel]

Hi

Yes, DDR3 IP, can be instantiated directly in MAX10 FPGA develop kit. Max 10 is using DDR3 UNIPHY IP where DDR3 UNIPHY IP is free IP that’s cover under free IP base suite

• https://www.intel.com/content/www/us/en/programmable/products/intellectual-property/design/ip-base-suite.html

But for TSE IP need a valid license. Please kindly contact your nearest Intel salesperson or distributor to purchase a valid license file. Alternatively, you could also request/ask for temporary evaluation license. Please find the contact for our sales and distributor from link below:

https://www.intel.com/content/www/us/en/partner/where-to-buy/overview.html

[AR_A_Intel]

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