MAX10 FPGA with JTAG issue and damaged FPGA

[SNatc]

Hello Everyone,

I am new to this forum. I am working with the MAX10 development board with the 10M50DAF484C6GES chip on it. I had no issues with the kit, I had programmed it couple of times with the sof file and also with the pof file on the internal flash. Last week it suddenly stopped working when I tried to reprogram the on-chip flash with a new design.

It failed during the programming process and the JTAG doesn't detect the FPGA anymore. It keeps throwing the following error "Error (209015): Can't configure device. Expected JTAG ID code 0x031050DD for device 1, but found JTAG ID code 0x00000000. Make sure the location of the target device on the circuit board matches the device's location in the device chain in the Chain Description File (.cdf)." If I try to autodetect the JTAG chain, the Quartus programmer says "UNKNOWN_NO_JTAG_ID".

I checked for the correct configuration settings like the JTAG sharing off, correct pin assignments, the cable connections, checked the voltage levels, probed the JTAG signals and everything seems to be in order, except the CONF_DONE (D20) led doesn't glow and if I bypass the VTAP10 it says "Unable to scan the chain". The previously programmed design also doesnt exist in the FLASH memory.

I suspect the FPGA got damaged somehow during programming. I might be missing some details, so please could someone give me your opinion on this. Have any of you faced a similiar problem like this ?

Thanks,

Sridi

[a_x_h_75]

Unfortunately, I don't think you're missing any detail. A previously working board no longer does. The JTAG ID code of all 0's is very ominous, perhaps as 'simple' as a blown JTAG buffer. However, there's no fixing that or any other fault in the device that may prevent the JTAG chain from functioning correctly. Without that you can't use the device.

Before writing it off do check all the power rails. Refer to the power tree on the 2nd page of the schematics and check all the rails it identifies are working, especially those that the FPGA relies on.

Cheers,

Alex