MAX10 devkit dual ethernet

[BJona]

Hi,

I am working on project using a full custom dual channel ethernet stack. This project is pretty similar from an older one I developed in the past using a Cyclone 3 E FPGA.

First, I had some timing problems using both of the ethernet channel on the MAX 10 devkit. 

 I added the sdc constraints provided by Intel . The timings are the same on both channels. 

Still, I can see on signaltap that a channel (A) get errors on the synchronisation frame x"5555..."  where the last byte is not x"D5". Thus, it won't work.

I change the Rx clock phase using the internal register of the marvell 88e1111. I still have the same issue.  

I am asking if this is even possible to get the two channels working together. 

[Deshi_Intel · Accepted solution]

Hi,

I believe the Max 10 dev kit has 2 RJ45 port so technically speaking it's capable to support 2 Ethernet ports.

Yet, you mentioned your Quartus design has some timing closure issue ? Then this could be the reason why your Ethernet traffic data transfer is corrupted.

• We need to ensure Quartus design meet timing closure to prevent it from facing potential functionality failure.

Thanks.

Regards,

dlim

[BJona]

Hi dlim,

thank you for your reply. As this issue has been solved internally, you can close the case.  It was not related to sdc constraints. Talking about sdc regarding RGMII DDIO, the one delivered with the devkit are really tight compared those given by the Application Note 477. I don't think it necessary.

Again, thank you dlim

Best regards,

John

[Deshi_Intel]

HI John,

I am glad your issue is resolved.

Alright, I am setting this case to closure.

Thanks.

Regards,

dlim