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MSI PCIE Interrupt set up using Avalon-MM PCIe Hard IP Core as a Qsys component...

dfowlkes
Beginner
664 Views

I'm confused about how to properly set up MSI interrupts across the PCIe interface using the Avalom-MM interface of the PCie Hard IP Core.  I am confident the PCIe host driver is enabling MSI's correctly because it worked with a previous adapter.  I have configured the FPGA's logic surrounding the core to enable the interrupts via the CRA port at address 0x0050.  This logic requests an interrupt by setting the core's RxmIrq<0> input to 1.  When this happens, I can read the interrupt status register at 0x0040 and see the correct bit set.  However, I don't ever see the Root Complex call my host-driver's interrupt handler.  I'm unsure about how the host driver is meant to acknowledge the interrupt using the CRA port.  How does the host driver access the interrupt status register to acknowledge the interrupt?  But, the first question is how do I make sure I've done everything to get the Root Complex to call my driver's ISR routine?  

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10 Replies
KhaiChein_Y_Intel
648 Views

Hi,


May I know which device you are using? Do you configure the IP as Root port or Native endpoint? You may generate the example design using the IP parameter GUI and refer to the software folder for reference.


Thanks

Best regards,

KhaiY


dfowlkes
Beginner
639 Views

Hello!

 

Yes, I am using a Stratix IV board with FPGA EP4SGX230KF40.

 

I'm designing an endpoint not a root port.  

 

Which example design should I be looking at that shows how to get the MSI working?

 

Daryl

KhaiChein_Y_Intel
629 Views

Hi Daryl,


The example design generation is only supported in the newer devices like Agilex, Stratix 10, Arria 10, etc.

For reference design, only Root port design is available.

https://fpgacloud.intel.com/devstore/platform/?search=MSI

https://rocketboards.org/foswiki/Projects/A10AVCV171PCIeRootPortWithMSI


Thanks

Best regards,

KhaiY


dfowlkes
Beginner
613 Views

Thanks KhaiY.  All I have to work with is the Stratix IV board.  I guess my real question relates to how an endpoint should invoke MSIs for the PCIe core that's compatible with that board via the Avalon-MM interface.  Do I use the physical RxmIrq<> lines and have the core generate the MemWr TLP upstream or should I use the msiintfc<> bus info and make use of the Txs slave interface?  I've tried the RxmIrq approach and saw the correct bit set in the CRA Interrupt Status Register (0x0040), but the root complex did not call the ISR of my host driver.  

 

Daryl

KhaiChein_Y_Intel
570 Views

Hi,


To enable MSI,

1. Set MSI Enable of MSI Control register, this bit is mapped to bit[16] of offset 0x50 in configuration space register. 

2. Set Interrupt Disable bit[10] of Command register at configuration space offset register 0x4 to disable legacy interrupt. 

3. Set bit[1] (Memory space) and bit[2] (Bus Master) of Command Register at configuration space offset register 0x4 to enable the ability to generate MSI message.  


Once users trigger the rxm_irq, the PCIe core will generates the interrupt message.

You may refer to Figure 4–13 for IP Compiler for PCI Express Avalon-MM Interrupt Propagation to the PCI Express Link

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pci_express.pdf


You may also refer to the below link for PCIe Interrupt Handling but the design is for Stratix V.

https://community.intel.com/t5/FPGA-Wiki/Handling-PCIe-Interrupts/ta-p/736044

https://community.intel.com/t5/FPGA-Wiki/Handling-PCIe-Interrupts/ta-p/736044


Thanks

Best regards,

KhaiY




dfowlkes
Beginner
537 Views

Hello KhaiY,

 

I have ensured that I have correctly performed steps 1-3 on the host.  I am also driving high the rxm_irq within the FPGA's design.  When I driver rxm_irq high then read the Interrupt Status Register using the CRA slave port at address 0x0040, I see the corresponding bit set.  However, I don't see an MSI message going upstream.  I still have the following questions:

 

1. How long should I drive the rxm_irq high in order to see an MSI sent upstream?

2. How is acknowledgement of the interrupt supposed to work since I'm not supposed to be writing to the CRA port from within my logic as the documentation claims it's "reserved for Root Complexes".

 

I see a lot of info for implementing MSI-x in the projects you referred me to, but not a lot regarding setting up MSI interrupts.  Are there example projects that will answer these questions for me?  I'm sure I'm missing something.

 

Many thanks for your responses and willingness to help.

 

Daryl  

KhaiChein_Y_Intel
519 Views

Hi,

 

1. There is no timing requirement specified in the user guide. If rxm_irq is asserted on consecutive cycles without the deassertion
of all interrupt inputs, no MSI message is sent for subsequent interrupts. To avoid losing interrupts, software must ensure that all interrupt sources are cleared for each MSI message received. 

2. You may refer to Figure 10-4 for the MSI Interrupt Signals Waveform. The minimum latency possible between app_msi_req and app_msi_ack
is one clock cycle.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pci_express.pdf

3. Unfortunately, there is a limited number of example design available for older devices. 

 

Thanks 

Best regards,

KhaiY

KhaiChein_Y_Intel
488 Views

Hi,


We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


Best regards,

KhaiY


dfowlkes
Beginner
477 Views

Hey KhaiY,

 

You helped me to see the flaw in my thinking.  I have the interrupts working now.  Thanks.

 

Daryl

KhaiChein_Y_Intel
467 Views

Hi,

I’m glad that it is working now, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Best regards,

KhaiY


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