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MT25Q Reset Pin wiring




the MT25Q configuration flash devices do have (as opposed former EPCQ devices) a reset pin.


I learned that reset of the QSPI flash might be an issue:







We intend to use the QSPI as a boot device for a Arria10 SX FPGA in FPGA Configuration via Active Serial x4.

Are there any known issues related to this setup?


We intend to use the following QSPI flash:

 ·        Ordering code:             MT25QU01GBBB8E12-0SIT

·        Manufacturer:              Micron

·        Memory Size:               1 Gb (128 MB)


The flash image file (non-CvP) (abc_top_epe.sof) 27 MByte (216Mbit), meaning that it would surpass the 128Mb boundary and require 4byte address mode.

Side question:

I could not find any information regarding 3byte or 4byte address modes in FPGA documentation. Are active serial images >128Mbit possilble at all and if so, how are these handled by the FPGA active serial loader?


An issue might occur when resetting the FPGA by software e.g. via the "remote update IP core".


What is the recommended wiring of the MT25Q reset pin?


I plan the implementation as follows:

BOARD_Reset "OR"-ed with an FPGA GPIO led to QSPI Reset Pin


This to be able to assert a QSPI reset from the FPGA ahead of a software FPGA reset.


I am looking forward to your recommendation.


Best regards,





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The KDB that you mention is related to QSPI Flash connected directly to the HPS pin and not the FPGA configuration pin. There will be no issue on connecting the MT25Q to FPGA configuration pin directly. You may refer to https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/compon... for the byte addressing mode.


For the reset pin, I would recommend you to weak-pull it so that the flash does not enter reset mode.