Mapping HPS GPI pin

[snehal_p]

Hello,

I need help in mapping the HPS GPI pin.

I'm using cyclone V SOC, for mapping HPS GPIO pins we can use mux table  in platform designer.

Similarly how can we map HPS GPI pin, I need to map HPSGPI9 pin.

Thanks,

snehal_p

[aikeu]

Hi snehal_p,

I do not understand your description properly, can elaborate more?

Thanks.

Regards,

Aik Eu

[snehal_p]

Hello Aik Eu,

For mapping HPSGPIO pins we can use mux table in platform designer, similarly can you please help with documentation/procedure for mapping HPSGPI pins.

HPS GPI is an input-only interface with 14-bit wide width. The interface share the same I/O pins with the HPS DDR SDRAM controller. Can you please help me with steps to map these pins in Quartus/Platform designer tool.

Please let me know if more information is needed.

Thanks,

snehal_p

[aikeu]

Hi snehal_p,

The HPS_GPI pins are different from other HPS peripheral pins or GPIOs. The HPS_GPI (referenced as HLGPI in Cyclone V TRM - chapter 22) are HPS dedicated pins and doesn't appear as ports on generated HDL entity. You can't even configure their usage via QSYS. These pins has fixed location and function and hence no assignment is needed.

Thanks.

Regards,

Aik Eu

[snehal_p]

Hello Aikeu,

We could configure it by enabling "Enable HLGPI interface" in FPGA interface configuration in hps parameter. But we are facing issue reading the interrupt/input in the c code/application code. 

Can you please help with the example code for reading hps gpi pin in c code.

If " These pins has fixed location and function and hence no assignment is needed." then can you please help me with the example code for reading HPSGPI pin.

Thanks,

snehal_p

[snehal_p]

Hello Aikeu,

Can we configure HPSGPI pins as interrupt?

Thanks,

snehal_p

[aikeu]

Hi snehal_p,

I will close this thread if no further question.

Thanks.

Regards,

Aik Eu