FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
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Max 10 internal decoupling capacitance


I am looking for some more information relating to power requirements of the 10M08 which I am designing into a system. (10M08SCU169C8G) I need additional information on the IC characteristics in order to run accurate power integrity simulations in Hyperlynx. The IBIS model supplied does not take package characteristics into account. In addition to this, there is the internal regulator (I am running off a 3.3V rail) I would like to know if there is any internal capacitance which may aid power integrity. Is there a model for the part I could use or additional guidelines for power integrity I could follow?


The decoupling network on the evaluation board is what I have used as a reference but this does not provide enough margin in my design at higher frequencies.



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Actually IBIS model do support the package information , Here is the link you can see more details about the ibis model.


About the device internal cap ...sorry we wont be able to provide the internal info of the chip , whereas i would suggest to use the PDN to get total de cap requirement .

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