May I use WYSIWYG for hardware or is it applicable only for synthesis?

[PSriv8]

May I use WYSIWYG for hardware or is it applicable only for synthesis?

I am trying to calculate the delay of a barrel shifter using the DE-115 FPGA board and digital oscilloscope. The shifter inputs are assigned to the FPGA switches (SW) and shifter outputs are assigned to the FPGA LEDs (LEDR). I have used a digital oscilloscope to tap the input and output signals simultaneously; therefore, the delay required by output after the change in input can be measured. The waveform suggests that the delay between input and output is always the same irrespective of the number of stages required by the shifter. This might happen due to the optimization of the design using logic elements LEs. Can I use the WYSIWYG feature for hardware testing so that the logic cells un-map the design into logic gates? 

Because Intel® Quartus® Prime Standard Edition User Guide mentioned the following:

"However, WYSIWYG primitive resynthesis can be done only when you use third-party synthesis tools."

Therefore, I am not sure whether the WYSIWYG feature can be used for hardware testing or not. Also,  is it available in the free version of Quartus?

[sstrell]

It is available in Lite and Standard editions, but like you say, it is only for when the results of a 3rd-party synthesis tool are brought into Quartus for place and route.

You could make use of timing reports in the Timing Analyzer to see the calculated delay from an input to an output.

#iwork4intel

[PSriv8]

Thank you for your reply. I still have few questions in mind, it might be very basic as I m still learning:
1. I didn't quite understand the meaning of using a 3rd party synthesis tool, coz as per my knowledge we have to use a third-party tool for synthesis (from cadence or synopsis etc) in order to calculate power, area and delay of a circuit. Does quartus have a synthesis tool for calculating the parameters like other synthesis tools can do?

2. I have designed a block diagram file (.bdf) with three stages of 2x1 muxes connected in series i.e. Output of stage 1 connected to input of stage 2 and output of stage 2 is connected to input of stage 3. The inputs are connected to switched of FPGA board and outputs are connected to LEDs. Now I connect the input switches and LEDs to a Digital oscilloscope and capture the waveform. The output changes after a delay of almost 12ns after it detects change in input.

I was expecting that taking output from various stages would require different time, for example: if tapping input from stage 1 and output from stage 1 requires time T, then tapping input from stage 1 and output from stage 2 should be 2T to and tapping input from stage 1 and output from stage 3 should be 3T. However, I am getting a delay of 12ns everytime irrespective of no of stages used. That is why I wanted to use the WYSIWYG feature. Could you please suggest.

[sstrell]

1) All the features you mentioned are built into Quartus.  Using a 3rd party synthesis tool is optional, and usually dictated by the company you work for I have found.  Built-in synthesis is usually more than sufficient for most designers and it's one less tool you have to learn/use/manage.

2) As mentioned, design optimization is probably causing this.  If you need specific delays for a design, you need to incorporate them into SDC timing constraints, such as set_max_delay and set_min_delay.  If you're not familiar with timing constraints and analysis, start here with this training:

https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1115.html

#iwork4intel

[PSriv8]

Thank you for your reply. I will explore the Quartus Synthesis feature to synthesize my design.

Regarding the SDC constraints, I have gone through the link you have shared and completed all the timing constraint sessions, which is very helpful. Thank you for sharing it.

1. However, I am not sure whether setting these timing constraints will provide me the actual delay required from input to output. We need to speculate the timing of various digital elements in advance to write the timing constraint, but I want to calculate the actual time required by the output (LED) to change its state once the input (Switch) is flipped. The design optimization is not letting me calculate the actual time on the FPGA board using DSO. Therefore I am trying to find out whether there is any feature available that could preserve the circuit as it is so that I can calculate the actual delay. I found the  'Preserve Registers' option as well, but I don't find it useful for preserving the delay of the circuit. 

2. As you have mentioned that Quartus already have a synthesis tool, can we calculate the processing time of a digital element such as gates/multiplexers/flip-flops, etc? For example, 

• In 65 nm technology, delay of a 2x1 mux = 50 ps (Measured using Cadence)

Can we calculate it using Quartus as well?

[sstrell]

In the Timing Analyzer, you could generate a path report from an input to an output to see all the delays along the path.  Is that what you want?

#iwork4intel

[PSriv8]

Yes, I want to calculate the actual delay required by a digital logic element without using a clock. I aim to design an asynchronous circuit, and I need to calculate the delay required by a 2x1 Mux to process the data when we change the value of the select line, delay of a logic gate (AND, OR, NOT, etc.), delay of decoder, etc. without using a global clock. This might be done using synthesis feature of the Quartus, I would be grateful if you can suggest me more on this.

However, I am trying to calculate the delay using FPGA hardware. For example, I have used the schematic for a 2x1 MUX with 2 inputs connected to the SW0 and SW1, the select line connected to SW2, and the output is connected to the LEDR0 of the FPGA board.  Now the changing the select line SW2 values will change the value of LEDR0. Can we calculate the delay of the 2x1 MUX by using a logic analyzer (or a digital oscilloscope) and calculating the delay required by LEDR0 to change its status once we change the value of the select line SW2?