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When I use the Intel Arria10 development board, I can generate the memory example design and select the Arria10 development board, then copy the memory IP to my design and use it. However, I don’t see the PAC card option to generate the memory example design. Is there a quick and reliable way to generate memory example design and IP for PAC card? Or do I have a go into the menu and set all the parameters for the memory? The later one is very tedious and it is easy to make mistake.
Thanks
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Dlim,
Yes, I am referring to the DDR4 memory on Intel A10 FX FPGA PAC card. I installed the acceleration stack SW but i still cannot find the memory IP. I see some other IPs such as DDR4_mm_bridge IP, Altera 10G Ethernet MAC IP, PLL IP, CRC32 IP... but I cannot find the memory IP. Any idea?
Thanks
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Dlim,
That's exactly where i get stuck. I have a design that is working on the A10 evaluation board and it uses memory, 10G MAC/PHyY and PCIe IPs. Now i need to port my design to the PAC card. How do I instantiate those IP? How do i call them and pass data from my logic to them? Is there any instructions or manuals on this?
Thanks
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