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Minimum power consumption of Cyclone 10LP.

I'm trying to find the minimum power consumption of a Cyclone 10LP. Specifically the 10CL025YU256C8G and 10CL025YU256I7G. The first is on an arrow cyc1000 board and the second is on an intel c10 eval board.

 

On the arrow, the minimum power consumption I can get is 100mA when powered by 5V USB. On the intel eval board, the best I can get is around 200mA. The arrow has all the leds turned off and the SDRAM in power off mode. The intel eval also has all the leds turned off, the ethernet phy in power down mode through MDIO, and the SDRAM spec says the RAM should go into low power mode automatically if the clock is stopped. On both boards I have a very simple design that does nothing but have static outputs with no clocks.

 

That the intel eval board takes 200mA is a bit surprising to me since it's about 1W of power even though nothing is happening. In fact, the power consumption of the board with a soft cpu running a benchmark isn't much higher then the simple design. The only thing I can think of that's using up that much power is the switching voltage regulators on the board, since I know that some switching regulators can use lot's of power even if the load is very small.

 

I'm looking into using these FPGAs in a device that would normally use a traditionally microcontroller and need to be able to put the device some kind of sleep mode that it can wake up from. Many controllers can consume less then 1mA @ 3.3V in sleep.

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Re: Minimum power consumption of Cyclone 10LP.

Intel FPGA dont have options as sleep mode : In general it is possible in flash based FPGA not the SRAM based. .

Can i know why your application would like to use FPGA ?

 

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Re: Minimum power consumption of Cyclone 10LP.

I can't give out too many details. I want a traditionally microcontroller functionality(hence the soft cpu) plus some custom peripherals. The custom peripherals is the reason for the FPGA.

 

This is interesting...

 

For some reason I assumed that like most modern digital hardware(based on MOSFETs), that if the signals are not changing that only low power is needed. So I was thinking I could implement sleep like functionality by turning off the clock to parts of the chip. In fact, the power analyzer in quartus says my simple test design should be using low power. I think the number is 0.080mW. Certainly no where near the 0.5W to 1W I'm seeing.

 

So would the M10 work better for my application, or does it also use lots of power even if nothing is changing?

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Re: Minimum power consumption of Cyclone 10LP.

Sorry, I mistyped. I believe quartus said the power estimate was 0.080W. Still that's under 1/5th of what I'm measuring.

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Re: Minimum power consumption of Cyclone 10LP.

We cant justify like that ; right way to chose the FPGA based on the EPE or Power Analyser result with premillary toggle rate.

from that static power calcualted values can be use as power dispiation when FPGA is doing nothing but powered ON.

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Re: Minimum power consumption of Cyclone 10LP.

I guess I'm a bit confused here. If that number is wrong, what kind of number should I be seeing?

 

One of the parts that confuses me the most is that why am I seeing very similar number between the two cases where the FPGA is doing nothing and the case where I have a soft cpu loaded that's running an intense benchmark? I would think the doing nothing number would be much lower then the doing something number.

 

The only thing I can think of off the top of my head is that the intel voltage regulators don't handle the low power drain case very well. That seems to be a common issue with many switching regulators. Some of the more advanced regulators will turn off the switching and go into a linear mode in the low drain case. I do have a few snofpga boards that use a M10 with a third party linear voltage regulator. I may try one of those boards with the do nothing case.

 

Do you have any other thoughts that might help?

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