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Hello.
I am working with C10GX eval kit.
I use AN829 AlalonMM DMA design as a starting point.
One MSI is working well. I want to use 4 ones.
PCIe hip is confugured to use 4 MSI.
In linux driver I try to allocate 4 vectors with pci_alloc_irq_verctors, but the system (Ubuntu 20.1) allocates only one vector.
I setup MSI conrol register (0x50) in the following way:
bit [0] (MSI Ena) = 1,
bits [3 : 1] = 010 -- multiple messages capable, 4 pcs, setup by IP core itself,
bits [6 : 4] = 010 -- multiply message enable, 4 messages
bit [7] = 1 -- 64 bit adddress capable.
But this does not help.
In addition, from FPGA side I monitor MSIControl_o signals. Normally, they should contain data from MSI control register, but in my case "multiply message enable " field contains 000 - only one message.
What is the right sequence of multiply MSI configuration?
Thank you.
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Hi,
Accordingly to PCIe user guide doc, you need to perform below 2 steps
- Turn on "Export MSI/MSI-X conduit interfaces" setting in PCIe IP to enable internal MSI interface bus
- Then create your own custom interrupt handler design to manage it
You can refer to page 99, chapter 8.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support of the user guide doc
Thanks.
Regards,
dlim
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This is true, if we are takng about FPGA side of the question.
But I am asking about driver side. As I understand, the allocation of irq vector should not be dependant on whether custom interrupt handler is realized in FPGA or not.
Isn't it?
Who is ressponsible to set bits [6 : 4] (multiply message enable) of conrol register (0x50) ?
Thank you.
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I see but sorry I am not familiar with driver side design implementation.
Hopefully other PCIe expert can jump into your forum thread to address your doubt
Regards,
dlim

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