Hi,I am trying to implement two NIOS II processors on the DE2 Board. My question: Is it possible to program both CPUs using one JTAG-UART via USB-Blaster. I tried this with an AVALON-Pipe, but this doesn't work. When I download the program I get "Leaving the processor paused", without any error. Also I tried to put two JTAG-UART in my SOPC project. There something happend, but I can't use the NIOS shell to get inforamtion using printf. And it seems not to work properly at all. I hope you can give me some hints. Thanks a lot for your help
The Nios II code downloading occurs over JTAG using the Nios II JTAG debug module. You can have multiple Nios II cores with one debug module each.The JTAG UART cannot be shared amongst multiple CPU cores (SOPC Builder should be preventing you from hooking it up this way). Instead you can use multiple JTAG UARTs and view them using multiple terminals. The multi-cpu collection allows you to set up this case and cycle through the various terminal outputs. I don't like this method so what I do instead is open multiple Nios II command shells and run nios-terminal in each shell passing in a different instance IDs. For example this is what I would use if I had two JTAG UARTs: nios2-terminal -i 0 nios2-terminal -i 1 The only tricky thing is that when you have an overlap in instance IDs, the tools will automatically re-assign the instance IDs. As a result it is up to you to figure out which one is which and pass in the ID accordingly.
Thanks for your answer.Now I have two JTAG-UARTs in my SOPC-project, which I attached, but I get this warnings: Warning: currently assigned JTAG instance ID 0 for cpu_1/jtag_debug_module is shared by cpu_2/jtag_debug_module. Reassigned to 1. Warning: currently assigned JTAG instance ID 0 for jtag_uart_0/avalon_jtag_slave is shared by jtag_uart_1/avalon_jtag_slave. Reassigned to 1. and when I try to run my NIOS II Project I get this message: Using cable "USB-Blaster [USB-0]", device 1, instance 0x01 Pausing target processor: OK Reading System ID at address 0x00081058: verified Initializing CPU cache (if present) OK Downloading 02000000 ( 0%) Downloaded 60KB in 1.0s (60.0KB/s) Verifying 02000000 ( 0%) Verified OK Leaving target processor paused Also I am a bit confused about where to put my Reset-/Exception vectors, at the moment both are for each cpu in the SDRAM ( CPU_1 0x200000 and 0x200020 cpu_2 0x210000 and 0x210020), furthermore .text,.rwdata, rodata and stack/heap memory are stored in SDRAM. What I need at the moment are 2 processors which share SRAM and SDRAM, to realize that I use two mutexs. Another question is, if it is possible to run one CPU at 100Mhz and the other at 50Mhz, sharing memory. Thanks again for your help Best wishes
Okay with the above configuration, and the option -i 0 it works, but still the stdout doesn't work and the warnings at the system generation are still there.
Those warnings are expected. SOPC Builder is re-assigning the ID values to make sure they are unique per IP core so passing -i 0 will access the first CPU and JTAG UART and -i 1 will access the second pair.If you have both processors sharing the same code memory then I would place the first CPU exception address at the beginning of the memory and the second CPU exception address at the middle of the memory. This should effectively cut the memory in half with each CPU using a half for code/data. Download your code and open a terminal to one CPU and JTAG UART at a time to make sure each works on it's own. Then you can bring up the entire system at once. Make sure to pass in the -i 0 or -i 1 to the nios2-terminal as well to make sure you select the correct UART to connect to. Another handy command I use all the time is 'jtagconfig -n'. This will print all programming cables, devices, and JTAG nodes hooked up to the JTAG server. The JTAG debug module should show up as 191046xx where 'xx' is the instance number. The JTAG UART should show up as 0C006Exx where 'xx' is the instance number. If you see other values in there they could be other things like Signaltap. Yes you can share memories on different clock domains. SOPC Builder will add clock crossing adapters automatically for you if the master and slave are on different clock domains. For code I recommend adding a clock crossing bridge between the CPU and RAM since it'll pipeline read and write commands. For more details you can find them in here: http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf