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Altera_Forum
Honored Contributor I
912 Views

NEEK Cyclone III edition problem

I am trying to create a simple project like Hello World or counter. I made a design but always getting error like;  

 

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Pausing target processor: OK 

Initializing CPU cache (if present) 

OK 

 

Downloading 02000000 ( 0%) 

Downloaded 20KB in 0.3s (66.6KB/s) 

 

Verifying 02000000 ( 0%) 

Verify failed between address 0x2000000 and 0x2004E0F 

Leaving target processor paused 

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Processor is already paused 

Initializing CPU cache (if present) 

OK 

 

Downloading 02000000 ( 0%) 

Downloaded 20KB in 0.3s (66.6KB/s) 

 

Verifying 02000000 ( 0%) 

Verify failed between address 0x2000000 and 0x2004E0F 

Leaving target processor paused 

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Processor is already paused 

Initializing CPU cache (if present) 

OK 

 

Downloading 02000000 ( 0%) 

Downloaded 20KB in 0.3s (66.6KB/s) 

 

Verifying 02000000 ( 0%) 

Verify failed between address 0x2000000 and 0x2004E0F 

Leaving target processor paused 

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Processor is already paused 

Initializing CPU cache (if present) 

OK 

 

Downloading 02000000 ( 0%) 

Downloaded 20KB in 0.3s (66.6KB/s) 

 

Verifying 02000000 ( 0%) 

Verify failed between address 0x2000000 and 0x2004E0F 

Leaving target processor paused 

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Processor is already paused 

Initializing CPU cache (if present) 

OK 

 

Downloading 02000000 ( 0%) 

Downloaded 20KB in 0.3s (66.6KB/s) 

 

Verifying 02000000 ( 0%) 

Verify failed between address 0x2000000 and 0x2004E0F 

Leaving target processor paused 

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 

Processor is already paused 

Initializing CPU cache (if present) 

OK 

 

Downloading 02000000 ( 0%) 

Downloaded 20KB in 0.3s (66.6KB/s) 

 

Verifying 02000000 ( 0%) 

Verify failed between address 0x2000000 and 0x2004E0F 

Leaving target processor paused 

 

 

I tried to attached my project file but i think it has big size to attach. Could you help me please..
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17 Replies
Altera_Forum
Honored Contributor I
45 Views

What type of memory is at address 0x2000000 in your system? 

SDRAM? Usually you get this error when the memory is not correctly working, because of bad clocking, wrong assignments, timing not met.
Altera_Forum
Honored Contributor I
45 Views

I attached my SOPC design. I tried to be very careful about pin assignments. 

 

Actually 0x200000 is the starting address of SDRAM
Altera_Forum
Honored Contributor I
45 Views

How much is pll_c2 clock frequency you are using to drive Nios and sdram? 

Is your design fully time constrained? Do you get any warning in the TQ reports? 

Which clock do you use to drive the sdram clk input? Have you tuned relative phase between sdram clock and pll_c2 in order to meet setup and hold requirements?
Altera_Forum
Honored Contributor I
45 Views

pll_c2 is 133 MHz.  

 

I have 47 warnings as result of the Time Quest Analysis. 

I fed sdram with pll_c2 on SOPC. İ did not tuned any phase. 

 

Here i added warnings of TQ analysis
Altera_Forum
Honored Contributor I
45 Views

These you posted are not TQ warnings. You must open TQ to get the complete reports about timing analysis. 

Anyway I can see in the underlying pane you have 6 "critical warnings": those are probably your real problem. Display them. I suppose they are sort of "timing not met"  

 

Running Nios at 133MHz on a CIII device can be very challenging. I don't mean it is impossible, but you must be smart in placing timing contraints and be sure to meet all of them after every recompilation. Moreover I don't think the device on the NEEK board is the fastest speed grade, so this won't help you. 

I suggest you start testing your design with maximum of 100MHz, which is a rather safe frequency and you should get all things working rather easily. 

 

Regarding the phase, usually you need to generate the clock feeding the external sdram clock pin with a small phase lead relative to the system clock of Nios and sdram controller. You make this with an additional pll output. The required phase lead can be derived from post fit analysis of delays of sdram signals and from sdram setup and hold specification. My rule of thumb is that 1ns phase lead is good with a 100MHz clock. 

 

Regards 

Cris
Altera_Forum
Honored Contributor I
45 Views

thanks for your replies. I am really new on FPGAs so i dont know much about them. İ will try to do what you said but i am not sure that i can make it. Thanks again and i will reply you when i tried what you told.

Altera_Forum
Honored Contributor I
45 Views

Hi Cris; 

 

I tried things you said. I changed pll frequency to 66.5 Mhz and delayed for 1 ns but still not works. Do you have any suggestions ?
Altera_Forum
Honored Contributor I
45 Views

First of all you must identify if your problem is with sdram or elsewhere. 

You can try running Nios code from onchip ram, so you exclude sdram timing problems and external connection. I think your fpga has enough onchip ram to fit the 20kB required by your test application. 

Steps: 

- add at least 32kb onchip ram with sopc builder  

- change Nios properties: start and exception vectors must point to onchip ram 

- generate the system 

- recompile fpga 

- change nios syslib properties so that code, stack, data are mapped to onchip ram 

- rebuild nios application 

 

When you are able to run the application with this modified system, you can focus on sdram. You can even use the application itself to perform some tests on sdram reading and writing data.
Altera_Forum
Honored Contributor I
45 Views

First of all, onchip ram is only 4kB on my kit.  

 

Today,I did something like you said and i was able to run counter example without sdram.
Altera_Forum
Honored Contributor I
45 Views

 

--- Quote Start ---  

First of all, onchip ram is only 4kB on my kit.  

 

--- Quote End ---  

 

Are you sure of this? afaik the CIII NEEK kit comes with a 3C25 device, which has 594kbits of memory: this means 66KBytes available to implement onchip ram. 

Probably you mean your current[/I][/I] sopc system has 4kB ram: you simply need to use sopc builder to increase the ram size or add another onchip ram component.
Altera_Forum
Honored Contributor I
45 Views

Anyway, thanks for help Cris72 but finally i gave up trying. i changed my kit. 

Now im working with DE2-70 and my design works.  

but i have new problem like, 

 

../hello_world.c: In function `test1_led': 

../hello_world.c:24: error: `IOWR_ALTERA_AVALON_PIO_DATA' undeclared (first use in this function) 

../hello_world.c:24: error: (Each undeclared identifier is reported only once 

../hello_world.c:24: error: for each function it appears in.) 

../hello_world.c:24: warning: left-hand operand of comma expression has no effect 

../hello_world.c:26: error: `PIO_RED_LED_BASE' undeclared (first use in this function) 

../hello_world.c:26: error: syntax error before "led_mask" 

../hello_world.c:28: warning: implicit declaration of function `usleep' 

../hello_world.c:30:2: warning: no newline at end of file 

../hello_world.c:30: error: syntax error at end of input 

 

my code; 

 

# include "system.h" 

# include "altera_avalon_pio_regs.h" 

# include "alt_types.h" 

void test1_led(void){ 

alt_u32 led_mask=0; 

while(1){ 

// green led control 

// red led control 

(IOWR_ALTERA_AVALON_PIO_DATA, led_mask); PIO_RED_LED_BASE 

// toggle led 

led_mask ^= 0xFFFFFFFF; 

// sleep 0.2 second 

usleep(200*1000); 

} // while
Altera_Forum
Honored Contributor I
45 Views

(IOWR_ALTERA_AVALON_PIO_DATA, led_mask); PIO_RED_LED_BASEWhat is this?!? :confused: 

 

It should be: 

IOWR_ALTERA_AVALON_PIO_DATA(PIO_RED_LED_BASE, led_mask);  

Also make sure that PIO_RED_LED_BASE is the correct define name for the pio (refer to system.h).
Altera_Forum
Honored Contributor I
45 Views

Actually, i dont know how to use variables in Nios II codes.  

 

in my SOPC design; 

 

"led" and "switch" are my pio names so can you help me how to read value or position of switches and how can i change values of leds.
Altera_Forum
Honored Contributor I
45 Views

Look into system.h file. 

You'll find the *_BASE defines for every sopc peripheral. 

Use those of led and switch pio ports to read and write pio status. 

For example if these were LED_BASE and SWITCH_BASE you write: 

 

IOWR_ALTERA_AVALON_PIO_DATA(LED_BASE, led_mask); to set led status 

sw = IORD_ALTERA_AVALON_PIO_DATA(SWITCH_BASE); to get switch status
Altera_Forum
Honored Contributor I
45 Views

#define LED_PIO_NAME "/dev/led_pio" 

# define LED_PIO_TYPE "altera_avalon_pio" 

# define LED_PIO_BASE 0x04404880 

# define LED_PIO_SPAN 16 

# define LED_PIO_DO_TEST_BENCH_WIRING 0 

# define LED_PIO_DRIVEN_SIM_VALUE 0x0000 

# define LED_PIO_HAS_TRI 0 

# define LED_PIO_HAS_OUT 1 

# define LED_PIO_HAS_IN 0 

# define LED_PIO_CAPTURE 0 

# define LED_PIO_EDGE_TYPE "NONE" 

# define LED_PIO_IRQ_TYPE "NONE" 

# define LED_PIO_BIT_CLEARING_EDGE_REGISTER 0 

# define LED_PIO_DATA_WIDTH 8 

# define LED_PIO_FREQ 85000000 

# define ALT_MODULE_CLASS_led_pio altera_avalon_pio 

 

in system.h file; led is defined as given above
Altera_Forum
Honored Contributor I
45 Views

Then, what's the problem? You have to write: 

IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE, led_mask); 

 

Examples: 

 

IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE, 0xffff); 

All LEDs on 

 

IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE, 0); 

All LEDs off 

 

 

IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE, 0x0003); 

Turn on LEDs connected to pio pins 0 and 1, off the others 

 

IOWR_ALTERA_AVALON_PIO_DATA(LED_PIO_BASE, 0x050c0); 

Turn on LEDs connected to pio pins 2,3,8,10, off the others
Altera_Forum
Honored Contributor I
45 Views

I just did succesfully before i read what you post. 

Now i am trying to read button values 

 

My fool. 

I added keys on my SOPC design but i was trying to control leds with switches. :) 

 

Thanks again Cris. I am appreciated.