FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
Announcements
The Intel sign-in experience has changed to support enhanced security controls. If you sign in, click here for more information.
5475 Discussions

NIOS Development Kit, Stratix Ed. Problem

Altera_Forum
Honored Contributor II
1,090 Views

I just got a Stratix board, and tried to test it. But I found none of the 10 LEDs and 8-segment LEDs are working properly. They are dark when I power up the board. I tried to program the FPGA to drive them with logic 1, nothing happened to them again. I also tried to reprogram the board to factory default, however, for some reason I cannot update the flash memory on the board. I don't know the status of the board, but I can still load the Stratix FPGA with no error. 

 

Can anyone help me on this? Thank you in advance. 

 

Forrest
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
380 Views

If you created a new hardware project then chances are your device options "unused I/O" are set to ground. There is an active low signal on that board that notifies the CPLD to send a new FPGA hardware image. So what might be happening is you download your design, that reconfig pin is unused and pulled low as a result, the then CPLD loads an image out of flash and sends that to the FPGA wiping out your original image. This happens very fast and makes it appear that your design isn't doing anything (I've done this a couple of times....:) ). To fix this try one of the following: 

 

1) Find the pin and pull it high in your design (the pin has a name similar to "reconfig_n") 

 

2) Go into the device options and under the unused I/O set them to "input tri-state". There is a pull-up on that signal so doing this will make sure it stays high. 

 

I hope that helps
Reply