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Altera_Forum
Honored Contributor I
871 Views

Need help running the PCIe to DDR3 SDRAM reference design

I've purchased an Altera Stratix IV GX FPGA development kit. I am trying to run the PCIe to DDR3 SDRAM reference design which I downloaded from: 

 

https://www.altera.com/support/software/download/refdesigns/ip/interface/dnl-pciexpress-ddr3-sdram.j... 

 

The FPGA device on my board is: EP4SGX230KF40C2 

 

The SOF file that comes with this design reference package is called top_example_chaining_top.sof. It seems as though this file is built for an ES (engineering silicon) device, so it doesn't work for the production level device mentioned above and when I try to re-build the SOF from the top level VHDL file, the place and route fails to meet timing requirements.  

 

Question: 

1. Can someone point me to where I can get a functional, already fully 

compiled SOF (SRAM Object File) for my device? 

2. If I have to recompile the design, can someone please confirm what the 

top level VHDL file is and other files I may have to add to the project. 

 

Thanks, 

 

Eric 

 

------------------------------------------------------- 

Electronics Engineer 

Microwave and Communication Systems Branch  

NASA Goddard Space Flight Center, Code 567 

8800 Greenbelt Road, Greenbelt, Maryland 20771, USA 

Building 25, Room S054, Mail Code 567.3 

Phone: (301)-286-3439 Email: eric.j.harris@nasa.gov 

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9 Replies
Altera_Forum
Honored Contributor I
120 Views

Hi, 

 

I recompiled the project with the nonES device and didnt get any errors? What errors did you see? 

 

The top level file can be seen in the quartus project, top_example_chaining_top.v
Altera_Forum
Honored Contributor I
120 Views

i did too, no errors but plenty of timing violations.

Altera_Forum
Honored Contributor I
120 Views

I'll have to go back and copy/paste the errors/warning, but in general, they are related to timing violations as thepancake noticed. 

 

A SOF file was built despite the timing violations but I wasn't able to get the application to work after programming the device. 

 

Please also address the following ... as I understand it, this PCIe to DDR3 application is supposed to measure the throughput of data being transferred across the PCIe bus from a PC to the DDR3 memory on the FPGA card ... but where exactly does the data on the PC side come from ... is the data generated from the PC's RAM or does it come from the PC's harddrive? 

 

Just a little more context here ... my eventual goal is measure the speed of transferring data from a set of raided solid state drives on my PC across a PCIe bus to the DDR3 memory on the Altera Stratix IV development board. I'm only using the aforementioned reference design to get a sense of how the PCI-Express-Mega-Core works and how fast data can be transferred. 

 

Please give feedback on this. 

 

Thanks, 

 

Eric
Altera_Forum
Honored Contributor I
120 Views

I suspect you're using Quartus 9.1? The timing analysis methodology for external memories changed in 9.1. To update the design, open the DDR3 IP in the mega wizard and regenerate it. Then run Analysis and Synthesis. Then run the <>_pin_assignments.tcl. I also disabled the D6 delay assignment on mem_clk as I wasnt sure why this would be required, probably something to do with early timing models or ES silicon. Then do a full compile. 

 

I just did this and it passes timing with the exception of one signal, coreclkout, looking in TQ I think this failure is a false path. 

 

I doubt the PC application is pulling data from the PCs harddrive, most apps like these just generate incremental or pseudo random data.  

 

AN431 has some info on the throughput. In this project the DDR3's BW is far greater than the PCIe, so i suspect the throughput is limited to the PCIe chipset and FPGA transceiver channels.
Altera_Forum
Honored Contributor I
120 Views

In reply to STD_LOGIC ... see the attached screenshot to get a sense of the timing violations I saw. 

 

Did you compile and build a SOF file for EP4SGX230KF40C2N (which is the specific non-engineering sample device I have)? Can you send me a copy so I can test it out? 

 

Just for clarification, when you say, " most apps like these just generate incremental or pseudo random data." ... do you mean that the application generates data in my PC's random access memory (RAM) then moves it across the PCIe bus to the DDR3 memory on the board? How does the application access and generate the data in RAM (the reference document doesn't explain this). 

 

Thanks, 

 

Eric 

------------------------------------------------------- 

Electronics Engineer 

Microwave and Communication Systems Branch  

NASA Goddard Space Flight Center, Code 567 

8800 Greenbelt Road, Greenbelt, Maryland 20771, USA 

Building 25, Room S054, Mail Code 567.3 

Phone: (301)-286-3439 Email: eric.j.harris@nasa.gov 

-------------------------------------------------------
Altera_Forum
Honored Contributor I
120 Views

zip of sof attached. 

 

I didnt get those timing violations, they look like DDR3 violations so I suspect you havent updated the IP and assignments. 

 

Sorry, i am not sure how the PC app works. It would surprise me if they intentionally would put the RAM in the path as this isnt the purpose of the design. I recommend filing a support request on this.
Altera_Forum
Honored Contributor I
120 Views

Wow, thanks ... we downloaded the sof file you provided and got the PCIe performance demo to work ... but we haven't got your previous timing related advice to work. Looks like we may need a license file for the PCIe Mega Core. 

 

Regards, 

 

Eric
Altera_Forum
Honored Contributor I
120 Views

I attached the qar of the edited project so you can see the assignments etc.

Altera_Forum
Honored Contributor I
120 Views

you shouldn't need a PCIe license if the design is using the hard IP.

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