Need sof file to run PCIe High Performance Reference Design

[Altera_Forum]

I am now trying to run the PCI Express High Performance Reference Design AN-456-1.2. (see http://www.altera.com/support/refdesigns/ip/interface/ref-pciexpress-hp.html) (http://www.altera.com/support/refdesigns/ip/interface/ref-pciexpress-hp.html%29). 

 I need to verify the performance of the reference design for PCI express, Gen2 rate, 5 Gb/s, x8 lanes, 128-bit configuration (see page 18 of description document).  However, I am getting the following error: CONF_DONE pin failed to go high in device 1. I think this problem is occurring because the sof file in the hip_gen2_x8_128 directory of this reference design package is not targeted to my device.  My Request: 1. Please send me a fully compiled sof file targeted to my Stratix IV GX  FPGA, EP4SGX230KF40C2N.  2. If possible, please send a flash file targeted to my device.  3. Also, please me the correct project directory with all the files needed  to recompile the design in case I need to regenerate the sof file  manually.  4. Please inform me if it is necessary to purchase any additional licenses  or SW to run this reference design.  5. The SW requirement state that I need to run Quartus II 9.0 SP2.   However, I am using a subscription version of Quartus II 9.1. Can I  assume that version 9.1 incorporates everything from version 9.0 +  the 9.0 SP2?  Of these requests,# 1 is most important, but please address the other questions.  Please note: the top.sof file currently in the hip_gen2_x8_128 directory is targeted to an engineering silicon (ES) device, not a production device like the one I actually have. Refer to the attached jpeg, "01-19-10 Conf done LED"  Thanks,  Eric  Electronics Engineer eric.j.harris@nasa.gov 301-286-3439