I have designed a board having Intel MAX10 10M25DAF484I7G device on the board. The board design has been frozen and i am trying to submit gerbers to manufacturing.
I was reading M10-ARCHITECTURE guide and i found that if we are using dedicated ADCs, then bank 1B cannot be used as GPIOs and Bank 8 have limitations on percentage of pins available for usage.
I am using the dedicated ADCs in my design and i have connected GPIOs on 1B bank (for 2.5V IO levels).
I have provided 3.3V voltage levels for VCCIO8 pins and i have used all the GPIOs available on Bank 8 for 3.3V IO levels.
Since the schematics are confidential, i cannot upload the schematics here. Please send me a email to my email id so that i can send the partial schematics for review purposes.
The matter is most urgent and i would be grateful if somebody can assist.
Thanks and regards,
Thanks for your inquiry.
You can follow the link below for schematic review:
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