Which is actual issue you are facing in your design? Would you mind to share a sample design that is causing the issue? It looks like your design is having assignment issue between LVDS and IOPLL. But we have to look into the design for detail understanding.
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Hi Eng Wei. Currently I still fail with this project. I have tried many solutions including test loopback on Module FMC_Loopback using Transceiver toolkit and have been successful. But when transmitting through the SFP port, there is an error. Can you point out what is the correct I/O configuration for the TXP and RXP pins? I don't know if you have tried the 1G baseX transmission test project using the Cyclone10Gx chip yet? Thank you very much!